Microsemi Corporation

ProASIC3 Field Programmable Gate Array (FPGA) IC 49 68-VFQFN Exposed Pad

General Description

ProASIC3，the third-generation family of Microsemi flash FPGAs, offers performance, density, and features beyond those

of the ProASIC^PLUS® family. Nonvolatile flash technology gives ProASIC3 devices the advantage of being a secure, low

power, single-chip solution that is Instant On. ProASIC3 is reprogrammable and offers time-to-market benefits at an

ASIC-level unit cost. These features enable designers to create high-density systems using existing ASIC or FPGA design

flows and tools.

ProASIC3 devices offer 1 kbit of on-chip, reprogrammable, nonvolatile FlashROM storage as well as clock conditioning

circuitry based on an integrated phase-locked loop (PLL). The A3P015 and A3P030 devices have no PLL or RAM support.

ProASIC3 devices have up to 1 million system gates, supported with up to 144 kbits of true dual-port SRAM and up to

300 user I/Os.

ProASIC3 devices support the ARM Cortex-M1 processor. The ARM-enabled devices have Microsemi ordering numbers

that begin with M1A3P (Cortex-M1) and do not support AES decryption.

Features and Benefits

• High Capacity

      15 K to 1 M System Gates

      Up to 144 Kbits of True Dual-Port SRAM

      Up to 300 User I/Os

• Reprogrammable Flash Technology

      130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Process

      Instant On Level 0 Support

      Single-Chip Solution

      Retains Programmed Design when Powered Off

• High Performance

      350 MHz System Performance

      3.3 V, 66 MHz 64-Bit PCI

• In-System Programming (ISP) and Security

      ISP Using On-Chip 128-Bit Advanced Encryption Standard (AES) Decryption (except ARM®-enabled ProASIC®3

      devices) via JTAG (IEEE 1532-compliant)

      FlashLock® to Secure FPGA Contents

• Low Power

      Core Voltage for Low Power

      Support for 1.5V-Only Systems

      Low-Impedance Flash Switches

• High-Performance Routing Hierarchy

      Segmented, Hierarchical Routing and Clock Structure

• Advanced I/O

      700 Mbps DDR,LVDS-Capable I/Os (A3P250 and above)

      1.5V, 1.8 V, 2.5 V,and 3.3V Mixed-Voltage Operation

      Wide Range Power Supply Voltage Support per JESD8-B, Allowing I/Os to Operate from 2.7 V to 3.6 V

      Bank-Selectable I/O Voltages—up to 4 Banks per Chip

      Single-Ended I/O Standards: LVTTL, LVCMOS 3.3V / 2.5V / 1.8V / 1.5V, 3.3V PCI / 3.3V PCI-X and LVCMOS 2.5V / 5.0V

      Input

      Differential I/O Standards: LVPECL，LVDS，B-LVDS, and M-LVDS (A3P250 and above)

      I/O Registers on Input, Output, and Enable Paths

      Hot-Swappable and Cold Sparing I/Os

      Programmable Output Slew Rate and Drive Strength

      Weak Pull-Up/-Down

      IEEE 1149.1 (JTAG) Boundary Scan Test

      Pin-Compatible Packages across the ProASIC3 Family

• Clock Conditioning Circuit (CCC) and PLL

      Six CCC Blocks, One with an Integrated PLL

      Configurable Phase-Shift, Multiply/Divide, Delay Capabilities and External Feedback

      Wide Input Frequency Range (1.5 MHz to 350 MHz)

• Embedded Memory

      1 Kbit of FlashROM User Nonvolatile Memory

      SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM Blocks (x1, x2, x4, x9, and x18 organizations)

      True Dual-Port SRAM (except x18)

• ARM Processor Support in ProASIC3 FPGAs

      M1 ProASIC3 Devices-ARM®Cortex®-M1 Soft Processor Available with or without Debug

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ProASIC3L Field Programmable Gate Array (FPGA) IC 151 36864 208-BFQFP

Clock Frequency Synthesis

Deriving clocks of various frequencies from a single reference clock is known as frequency synthesis.The PLL has an input

frequency range from 1.5 to 350 MHz. This frequency is automatically divideddown to a range between 1.5 MHz and

5.5 MHz by input dividers (not shown in Figure 4-19 on page 100)between PLL macro inputs and PLL phase detector

inputs. The VCO output is capable of an outputrange from 24 to 350 MHz. With dividers before the input to the PLL core

and following the VCO outputs,the VCO output frequency can be divided to provide the final frequency range from 0.75

to 350 MHz.Using SmartGen, the dividers are automatically set to achieve the closest possible matches to thespecified

output frequencies.

Users should be cautious when selecting the desired PLL input and output frequencies and the I/O bufferstandard used

to connect to the PLL input and output clocks. Depending on the I/O standards used forthe PLL input and output clocks,

the I/O frequencies have different maximum limits. Refer to the familydatasheets for specifications of maximum I/O

frequencies for supported I/O standards. Desired PLL inputor output frequencies will not be achieved if the selected

frequencies are higher than the maximum I/Ofrequencies allowed by the selected I/O standards. Users should be careful

when selecting the I/Ostandards used for PLL input and output clocks. Performing post-layout simulation can help detect

thistype of error, which will be identified with pulse width violation errors. Users are strongly encouraged toperform

post-layout simulation to ensure the I/O standard used can provide the desired PLL input oroutput frequencies. Users can

also choose to cascade PLLs together to achieve the high frequenciesneeded for their applications. Details of cascading

PLLs are discussed in the "Cascading CCCs" sectionon page 125.

In SmartGen, the actual generated frequency (under typical operating conditions) will be displayedbeside the requested

output frequency value. This provides the ability to determine the exact frequencythat can be generated by SmartGen, in

real time. The log file generated by SmartGen is a useful tool indetermining how closely the requested clock frequencies

match the user specifications. For example,assume a user specifies 101 MHz as one of the secondary output frequencies.

If the best outputfrequency that could be achieved were 100 MHz, the log file generated by SmartGen would indicate

theactual generated frequency

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Fusion® Field Programmable Gate Array (FPGA) IC 60 27648 180-WFQFN Dual Rows, Exposed Pad

General Description

The Fusion family, based on the highly successful ProASIC®3 and ProASIC3E flash FPGA architecture,has been designed

as a high-performance, programmable, mixed signal platform. By combining anadvanced flash FPGA core with flash

memory blocks and analog peripherals, Fusion devicesdramatically simplify system design and, as a result, dramatically

reduce overall system cost and boardspace.

The state-of-the-art flash memory technology offers high-density integrated flash memory blocks,enabling savings in

cost, power, and board area relative to external flash solutions, while providingincreased flexibility and performance. The

flash memory blocks and integrated analog peripherals enabletrue mixed-mode programmable logic designs. Two

examples are using an on-chip soft processor toimplement a fully functional flash MCU and using high-speed FPGA logic

to offer system and powersupervisory capabilities. Instant On, and capable of operating from a single 3.3 V supply, the

Fusionfamily is ideally suited for system management and control applications.

The devices in the Fusion family are categorized by FPGA core density. Each family member containsmany peripherals,

including flash memory blocks, an analog-to-digital-converter (ADC), high-driveoutputs, both RC and crystal oscillators,

and a real-time counter (RTC). This provides the user with ahigh level of flexibility and integration to support a wide

variety of mixed signal applications. The flashmemory block capacity ranges from 2 Mbits to 8 Mbits. The integrated

12-bit ADC supports up to 30independently configurable input channels. 

The on-chip crystal and RC oscillators work in conjunction with the integrated phase-locked loops (PLLs)to provide

clocking support to the FPGA array and on-chip resources. In addition to supporting typicalRTC uses such as watchdog

timer, the Fusion RTC can control the on-chip voltage regulator to powerdown the device (FPGA fabric, flash memory

block, and ADC), enabling a low power standby mode.

The Fusion family offers revolutionary features, never before available in an FPGA. The nonvolatile flashtechnology gives

the Fusion solution the advantage of being a highly secure, low power, single-chipsolution that is Instant On. Fusion is

reprogrammable and offers time-to-market benefits at an ASIC-levelunit cost. These features enable designers to create

high-density systems using existing ASIC or FPGAdesign flows and tools.

Features and Benefits

• High-Performance Reprogrammable FlashTechnology

      Advanced 130-nm, 7-Layer Metal, Flash-Based CMOSProcess

      Nonvolatile, Retains Program when Powered Off

      Instant On Single-Chip Solution

      350 MHz System Performance

• Embedded Flash Memory

      User Flash Memory–2 Mbits to 8 Mbits

      – Configurable 8-, 16-, or 32-Bit Datapath

      – 10 ns Access in Read-Ahead Mode

      1 Kbit of Additional FlashROM

• Integrated A/D Converter (ADC) and Analog I/O

      Up to 12-Bit Resolution and up to 600 Ksps

      Internal 2.56 V or External Reference Voltage

      ADC: Up to 30 Scalable Analog Input Channels

      High-Voltage Input Tolerance: –10.5 V to +12 V

      Current Monitor and Temperature Monitor Blocks

      Up to 10 MOSFET Gate Driver Outputs

      – P- and N-Channel Power MOSFET Support

      – Programmable 1, 3, 10, 30 µA, and 20 mA DriveStrengths

      ADC Accuracy is Better than 1%

• On-Chip Clocking Support

      Internal 100 MHz RC Oscillator (accurate to 1%)

      Crystal Oscillator Support (32 KHz to 20 MHz)

      Programmable Real-Time Counter (RTC)

      6 Clock Conditioning Circuits (CCCs) with 1 or 2 Integrated PLLs

      – Phase Shift, Multiply/Divide, and Delay Capabilities

      – Frequency: Input 1.5–350 MHz, Output 0.75–350 MHz

• Low Power Consumption

      Single 3.3 V Power Supply with On-Chip 1.5 V Regulator

      Sleep and Standby Low-Power Modes

• In-System Programming (ISP) and Security

      ISP with 128-Bit AES via JTAG

      FlashLock® Designed to Protect FPGA Contents

• Advanced Digital I/O

      1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation

      Bank-Selectable I/O Voltages – Up to 5 Banks per Chip

      Single-Ended I/O Standards: LVTTL, LVCMOS 3.3V/2.5V/1.8V/1.5V,3.3V PCI/3.3V PCI-X, and LVCMOS 2.5V/5.0 V Input

      Differential I/O Standards: LVPECL, LVDS, B-LVDS,M-LVDS

      – Built-In I/O Registers

      – 700 Mbps DDR Operation

      Hot-Swappable I/Os

      Programmable Output Slew Rate, Drive Strength, and Weak Pull-Up/Down Resistor

      Pin-Compatible Packages across the Fusion® FamilySRAMs and FIFOs

      Variable-Aspect-Ratio 4,608-Bit SRAM Blocks (×1, ×2,×4, ×9, and ×18 organizations available)

      True Dual-Port SRAM (except ×18)

      Programmable Embedded FIFO Control Logic

• Soft ARM Cortex-M1 Fusion Devices (M1)

      ARM® Cortex-™M1–Enabled

• Pigeon Point ATCA IP Support (P1)

      Targeted to Pigeon Point® Board ManagementReference (BMR) Starter Kits

      Designed in Partnership with Pigeon Point Systems

      ARM Cortex-M1 Enabled

• MicroBlade Advanced Mezzanine Card Support (U1)

      Targeted to Advanced Mezzanine Card (AdvancedMC™Designs)

      Designed in Partnership with MicroBlade

      8051-Based Module Management Controller (MMC)

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