HCS12X HCS12X Microcontroller IC 16-Bit 40MHz 64KB (64K x 8) FLASH 64-LQFP (10x10)

Catalog  

• Product Introduction

  To provide the most up-to-date information, the document revision on the World Wide Web is the most

  current. A printed copy may be an earlier revision. To verify you have the latest information available,

  refer to freescale.com.

  This document contains information for the complete S12XS Family and thus includes a set of separate

  flash (FTMR) module sections to cover the whole family. A full list of family members and options is

  included in the appendices.

  This document contains information for all constituent modules, with the exception of the CPU. For CPU

  information please refer to CPU12XV1 in the CPU12/CPU12X Reference Manual.

• Specifications

  Features of the S12XS Family are listed here. Please see Table D-1 for memory options and Table D-2 for

  the peripheral features that are available on the different family members.

  • 16-bit CPU12X

  — Upward compatible with S12 instruction set with the exception of five Fuzzy instructions

  (MEM, WAV, WAVR, REV, REVW) which have been removed

  — Enhanced indexed addressing

  — Access to large data segments independent of PPAGE

  Device Overview S12XS Family

  S12XS Family Reference Manual, Rev. 1.13

  20 Freescale Semiconductor

  • INT (interrupt module)

  — Seven levels of nested interrupts

  — Flexible assignment of interrupt sources to each interrupt level.

  — External non-maskable high priority interrupt (XIRQ)

  — The following inputs can act as Wake-up Interrupts

  – IRQ and non-maskable XIRQ

  – CAN receive pins

  – SCI receive pins

  – Depending on the package option up to 20 pins on ports J, H and P configurable as rising or

  falling edge sensitive

  • MMC (module mapping control)

  • DBG (debug module)

  — Monitoring of CPU bus with tag-type or force-type breakpoint requests

  — 64 x 64-bit circular trace buffer captures change-of-flow or memory access information

  • BDM (background debug mode)

  • OSC_LCP (oscillator)

  — Low power loop control Pierce oscillator utilizing a 4MHz to 16MHz crystal

  — Good noise immunity

  — Full-swing Pierce option utilizing a 2MHz to 40MHz crystal

  — Transconductance sized for optimum start-up margin for typical crystals

  • IPLL (Internally filtered, frequency modulated phase-locked-loop clock generation)

  — No external components required

  — Configurable option to spread spectrum for reduced EMC radiation (frequency modulation)

  • CRG (clock and reset generation)

  — COP watchdog

  — Real time interrupt

  — Clock monitor

  — Fast wake up from STOP in self clock mode

  • Memory Options

  — 64, 128 and 256 Kbyte Flash

  — Flash General Features

  – 64 data bits plus 8 syndrome ECC (Error Correction Code) bits allow single bit failure

  correction and double fault detection

  – Erase sector size 1024 bytes

  – Automated program and erase algorithm

  – Protection scheme to prevent accidental program or erase

  – Security option to prevent unauthorized access

  – Sense-amp margin level setting for reads

  — 4 and 8 Kbyte Data Flash space

• Datasheet PDF

https://rocelec.widen.net/view/pdf/xlz4a1mesi/FSCLS07362-1.pdf?t.download=true&u=5oefqw

Application Q＆A

Q:Mc9S12xs128 Is the microcontroller only one timer can use?can run both timers at once？

Reference answer：Two cars can be run together at the same time。

Pin Assignments 64-pin LQFP Package

How read the label of the NXP chip？

What is the naming rules of NXP microcontrollers?

See the video for the answer--

PDF

Refer to alternative Part：

MC9S12XS128CAE

MC9S12XS256CAE

56800E 56F8xxx Microcontroller IC 16-Bit 60MHz 256KB (128K x 16) FLASH 128-LQFP (14x20)

Device Description

The 56F8355 and 56F8155 are members of the 56800E core-based family of controllers. It combines, on

a single chip, the processing power of a Digital Signal Processor (DSP) and the functionality of a

microcontroller with a flexible set of peripherals to create an extremely cost-effective solution. Because

of its low cost, configuration flexibility, and compact program code, the 56F8355 and 56F8155 are

well-suited for many applications. The devices include many peripherals that are especially useful for

motion control, smart appliances, steppers, encoders, tachometers, limit switches, power supply and

control, automotive control (56F8355 only), engine management, noise suppression, remote utility

metering, industrial control for power, lighting, and automation applications.

The 56800E core is based on a Harvard-style architecture consisting of three execution units operating in

parallel, allowing as many as six operations per instruction cycle. The MCU-style programming model and

optimized instruction set allow straightforward generation of efficient, compact DSP and control code.

The instruction set is also highly efficient for C/C++ Compilers to enable rapid development of optimized

control applications. 

The 56F8355 and 56F8155 support program execution from internal memories. Two data operands can be

accessed from the on-chip data RAM per instruction cycle. These devices also provide two external

dedicated interrupt lines and up to 49 General Purpose Input/Output (GPIO) lines, depending on peripheral

configuration.

56F8355 Features

The 56F8355 controller includes 256KB of Program Flash and 8KB of Data Flash (each programmable

through the JTAG port) with 4KB of Program RAM and 16KB of Data RAM. A total of 16KB of Boot

Flash is incorporated for easy customer inclusion of field-programmable software routines that can be used

to program the main Program and Data Flash memory areas. Both Program and Data Flash memories can

be independently bulk erased or erased in page sizes. Program Flash page erase size is 1KB. Boot and Data

Flash page erase size is 512 bytes. The Boot Flash memory can also be either bulk or page erased.

A key application-specific feature of the 56F8355 is the inclusion of two Pulse Width Modulator (PWM)

modules. These modules each incorporate three complementary, individually programmable PWM signal

output pairs (each module is also capable of supporting six independent PWM functions, for a total of 12

PWM outputs) to enhance motor control functionality. Complementary operation permits programmable

dead time insertion, distortion correction via current sensing by software, and separate top and bottom

output polarity control. The up-counter value is programmable to support a continuously variable PWM

frequency. Edge-aligned and center-aligned synchronous pulse width control (0% to 100% modulation) is

supported. The device is capable of controlling most motor types: ACIM (AC Induction Motors); both

BDC and BLDC (Brush and Brushless DC motors); SRM and VRM (Switched and Variable Reluctance

Motors); and stepper motors. The PWMs incorporate fault protection and cycle-by-cycle current limiting

with sufficient output drive capability to directly drive standard optoisolators. A “smoke-inhibit”,

write-once protection feature for key parameters is also included. A patented PWM waveform distortion

correction circuit is also provided. Each PWM is double-buffered and includes interrupt controls to permit

integral reload rates to be programmable from 1 to 16. The PWM modules provide a reference output to

synchronize the Analog-to-Digital Converters through two channels of Quad Timer C.

The 56F8355 incorporates two Quadrature Decoders capable of capturing all four transitions on the

two-phase inputs, permitting generation of a number proportional to actual position. Speed computation

capabilities accommodate both fast- and slow-moving shafts. An integrated watchdog timer in the

Quadrature Decoder can be programmed with a time-out value to alert when no shaft motion is detected.

Each input is filtered to ensure only true transitions are recorded.

This controller also provides a full set of standard programmable peripherals that include two Serial

Communications Interfaces (SCIs); two Serial Peripheral Interfaces (SPIs); and four Quad Timers. Any of

these interfaces can be used as General-Purpose Input/Outputs (GPIOs) if that function is not required. A

Flex Controller Area Network (FlexCAN) interface (CAN Version 2.0 B-compliant) and an internal

interrupt controller are included on the 56F8355.

How read the label of the NXP chip？What is the naming rules of NXP microcontrollers?