Intel

Cyclone® Field Programmable Gate Array (FPGA) IC 65 59904 2910 100-TQFP

Introduction

The Cyclone® field programmable gate array family is based on a 1.5-V,

0.13-μm, all-layer copper SRAM process, with densities up to

20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like

phase-locked loops (PLLs) for clocking and a dedicated double data rate

(DDR) interface to meet DDR SDRAM and fast cycle RAM (FCRAM)

memory requirements, Cyclone devices are a cost-effective solution for

data-path applications. Cyclone devices support various I/O standards,

including LVDS at data rates up to 640 megabits per second (Mbps), and

66- and 33-MHz, 64- and 32-bit peripheral component interconnect (PCI),

for interfacing with and supporting ASSP and ASIC devices. Altera also

offers new low-cost serial configuration devices to configure Cyclone

devices.

Features

The Cyclone device family offers the following features:

■ 2,910 to 20,060 LEs, see Table 1–1

■ Up to 294,912 RAM bits (36,864 bytes)

■ Supports configuration through low-cost serial configuration device

■ Support for LVTTL, LVCMOS, SSTL-2, and SSTL-3 I/O standards

■ Support for 66- and 33-MHz, 64- and 32-bit PCI standard

■ High-speed (640 Mbps) LVDS I/O support

■ Low-speed (311 Mbps) LVDS I/O support

■ 311-Mbps RSDS I/O support

■ Up to two PLLs per device provide clock multiplication and phase

shifting

■ Up to eight global clock lines with six clock resources available per

logic array block (LAB) row

■ Support for external memory, including DDR SDRAM (133 MHz),

FCRAM, and single data rate (SDR) SDRAM

■ Support for multiple intellectual property (IP) cores, including

Altera® MegaCore® functions and Altera Megafunctions Partners

Program (AMPPSM) megafunctions. 

Chip Altera Cyclone naming rules，Chinese chip Will replace it

PDF

Cyclone® Field Programmable Gate Array (FPGA) IC 249 78336 4000 324-BGA

Introduction

The Cyclone® field programmable gate array family is based on a 1.5-V,

0.13-μm, all-layer copper SRAM process, with densities up to

20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like

phase-locked loops (PLLs) for clocking and a dedicated double data rate

(DDR) interface to meet DDR SDRAM and fast cycle RAM (FCRAM)

memory requirements, Cyclone devices are a cost-effective solution for

data-path applications. Cyclone devices support various I/O standards,

including LVDS at data rates up to 640 megabits per second (Mbps), and

66- and 33-MHz, 64- and 32-bit peripheral component interconnect (PCI),

for interfacing with and supporting ASSP and ASIC devices. Altera also

offers new low-cost serial configuration devices to configure Cyclone

devices.

Features

The Cyclone device family offers the following features:

■ 2,910 to 20,060 LEs, see Table 1–1

■ Up to 294,912 RAM bits (36,864 bytes)

■ Supports configuration through low-cost serial configuration device

■ Support for LVTTL, LVCMOS, SSTL-2, and SSTL-3 I/O standards

■ Support for 66- and 33-MHz, 64- and 32-bit PCI standard

■ High-speed (640 Mbps) LVDS I/O support

■ Low-speed (311 Mbps) LVDS I/O support

■ 311-Mbps RSDS I/O support

■ Up to two PLLs per device provide clock multiplication and phase

shifting

■ Up to eight global clock lines with six clock resources available per

logic array block (LAB) row

■ Support for external memory, including DDR SDRAM (133 MHz),

FCRAM, and single data rate (SDR) SDRAM

■ Support for multiple intellectual property (IP) cores, including

Altera® MegaCore® functions and Altera Megafunctions Partners

Program (AMPPSM) megafunctions. 

Chip Altera Cyclone naming rules，Chinese chip Will replace it

PDF

Cyclone® Field Programmable Gate Array (FPGA) IC 173 239616 12060 240-BFQFP

Introduction

The Cyclone® field programmable gate array family is based on a 1.5-V,

0.13-μm, all-layer copper SRAM process, with densities up to

20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like

phase-locked loops (PLLs) for clocking and a dedicated double data rate

(DDR) interface to meet DDR SDRAM and fast cycle RAM (FCRAM)

memory requirements, Cyclone devices are a cost-effective solution for

data-path applications. Cyclone devices support various I/O standards,

including LVDS at data rates up to 640 megabits per second (Mbps), and

66- and 33-MHz, 64- and 32-bit peripheral component interconnect (PCI),

for interfacing with and supporting ASSP and ASIC devices. Altera also

offers new low-cost serial configuration devices to configure Cyclone

devices.

Features

The Cyclone device family offers the following features:

■ 2,910 to 20,060 LEs, see Table 1–1

■ Up to 294,912 RAM bits (36,864 bytes)

■ Supports configuration through low-cost serial configuration device

■ Support for LVTTL, LVCMOS, SSTL-2, and SSTL-3 I/O standards

■ Support for 66- and 33-MHz, 64- and 32-bit PCI standard

■ High-speed (640 Mbps) LVDS I/O support

■ Low-speed (311 Mbps) LVDS I/O support

■ 311-Mbps RSDS I/O support

■ Up to two PLLs per device provide clock multiplication and phase

shifting

■ Up to eight global clock lines with six clock resources available per

logic array block (LAB) row

■ Support for external memory, including DDR SDRAM (133 MHz),

FCRAM, and single data rate (SDR) SDRAM

■ Support for multiple intellectual property (IP) cores, including

Altera® MegaCore® functions and Altera Megafunctions Partners

Program (AMPPSM) megafunctions. 

Chip Altera Cyclone naming rules，Chinese chip Will replace it

PDF

Cyclone® Field Programmable Gate Array (FPGA) IC 173 239616 12060 240-BFQFP

Introduction

The Cyclone® field programmable gate array family is based on a 1.5-V,

0.13-μm, all-layer copper SRAM process, with densities up to

20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like

phase-locked loops (PLLs) for clocking and a dedicated double data rate

(DDR) interface to meet DDR SDRAM and fast cycle RAM (FCRAM)

memory requirements, Cyclone devices are a cost-effective solution for

data-path applications. Cyclone devices support various I/O standards,

including LVDS at data rates up to 640 megabits per second (Mbps), and

66- and 33-MHz, 64- and 32-bit peripheral component interconnect (PCI),

for interfacing with and supporting ASSP and ASIC devices. Altera also

offers new low-cost serial configuration devices to configure Cyclone

devices.

Features

The Cyclone device family offers the following features:

■ 2,910 to 20,060 LEs, see Table 1–1

■ Up to 294,912 RAM bits (36,864 bytes)

■ Supports configuration through low-cost serial configuration device

■ Support for LVTTL, LVCMOS, SSTL-2, and SSTL-3 I/O standards

■ Support for 66- and 33-MHz, 64- and 32-bit PCI standard

■ High-speed (640 Mbps) LVDS I/O support

■ Low-speed (311 Mbps) LVDS I/O support

■ 311-Mbps RSDS I/O support

■ Up to two PLLs per device provide clock multiplication and phase

shifting

■ Up to eight global clock lines with six clock resources available per

logic array block (LAB) row

■ Support for external memory, including DDR SDRAM (133 MHz),

FCRAM, and single data rate (SDR) SDRAM

■ Support for multiple intellectual property (IP) cores, including

Altera® MegaCore® functions and Altera Megafunctions Partners

Program (AMPPSM) megafunctions. 

Chip Altera Cyclone naming rules，Chinese chip Will replace it

PDF

Cyclone® Field Programmable Gate Array (FPGA) IC 185 92160 5980 256-BGA

Introduction

The Cyclone® field programmable gate array family is based on a 1.5-V,

0.13-μm, all-layer copper SRAM process, with densities up to

20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like

phase-locked loops (PLLs) for clocking and a dedicated double data rate

(DDR) interface to meet DDR SDRAM and fast cycle RAM (FCRAM)

memory requirements, Cyclone devices are a cost-effective solution for

data-path applications. Cyclone devices support various I/O standards,

including LVDS at data rates up to 640 megabits per second (Mbps), and

66- and 33-MHz, 64- and 32-bit peripheral component interconnect (PCI),

for interfacing with and supporting ASSP and ASIC devices. Altera also

offers new low-cost serial configuration devices to configure Cyclone

devices.

Features

The Cyclone device family offers the following features:

■ 2,910 to 20,060 LEs, see Table 1–1

■ Up to 294,912 RAM bits (36,864 bytes)

■ Supports configuration through low-cost serial configuration device

■ Support for LVTTL, LVCMOS, SSTL-2, and SSTL-3 I/O standards

■ Support for 66- and 33-MHz, 64- and 32-bit PCI standard

■ High-speed (640 Mbps) LVDS I/O support

■ Low-speed (311 Mbps) LVDS I/O support

■ 311-Mbps RSDS I/O support

■ Up to two PLLs per device provide clock multiplication and phase

shifting

■ Up to eight global clock lines with six clock resources available per

logic array block (LAB) row

■ Support for external memory, including DDR SDRAM (133 MHz),

FCRAM, and single data rate (SDR) SDRAM

■ Support for multiple intellectual property (IP) cores, including

Altera® MegaCore® functions and Altera Megafunctions Partners

Program (AMPPSM) megafunctions. 

Chip Altera Cyclone naming rules，Chinese chip Will replace it

PDF

Cyclone® 10 LP Field Programmable Gate Array (FPGA) IC 176 423936 10320 256-LFBGA

Operating Conditions

When Intel Cyclone 10 LP devices are implemented in a system, they are rated according to a set of defined parameters.

To maintain the highest possible performance and reliability of Intel Cyclone 10 LP devices, you must consider the operating

requirements described in this document. Intel Cyclone 10 LP devices are offered in commercial, industrial, extended

industrial and, automotive grades as follows:

• –6 (fastest) and –8 speed grades for commercial devices

• –7 and –8 speed grades for industrial devices

• –7 speed grade for automotive devices

Intel Cyclone 10 LP devices are offered in the following core voltages:

• Lower core voltage option (1.0 V)—"Z": For –I8 speed grade

• Standard core voltage option (1.2 V)—"Y": For –C6, –C8, –I7, and –A7 speed grades

A prefix associated with the operating temperature range is attached to the speed grades:

• Commercial with a "C" prefix: –C6, –C8

• Industrial with an "I" prefix: –I7, –I8

• Automotive with an "A" prefix: –A7

How to choose FPGA for your project?

Cyclone® II Field Programmable Gate Array (FPGA) IC 85 165888 8256 144-LQFP

Introduction

Following the immensely successful first-generation Cyclone® device

family, Altera® Cyclone II FPGAs extend the low-cost FPGA density

range to 68,416 logic elements (LEs) and provide up to 622 usable I/O

pins and up to 1.1 Mbits of embedded memory. Cyclone II FPGAs are

manufactured on 300-mm wafers using TSMC's 90-nm low-k dielectric

process to ensure rapid availability and low cost. By minimizing silicon

area, Cyclone II devices can support complex digital systems on a single

chip at a cost that rivals that of ASICs. Unlike other FPGA vendors who

compromise power consumption and performance for low-cost, 

Altera’s latest generation of low-cost FPGAs—Cyclone II FPGAs, offer 60% 

higher performance and half the power consumption of competing 90-nm FPGAs. 

The low cost and optimized feature set of Cyclone II FPGAs make them ideal 

solutions for a wide array of automotive, consumer,communications, video processing, 

test and measurement, and other end-market solutions. Reference designs, 

system diagrams, and IP, found at www.altera.com, are available to help

 you rapidly develop complete end-market solutions using Cyclone II FPGAs.

Low-Cost Embedded Processing Solutions

Cyclone II devices support the Nios II embedded processor which allows

you to implement custom-fit embedded processing solutions. Cyclone II

devices can also expand the peripheral set, memory, I/O, or performance

of embedded processors. Single or multiple Nios II embedded processors

can be designed into a Cyclone II device to provide additional

co-processing power or even replace existing embedded processors in

your system. Using Cyclone II and Nios II together allow for low-cost,

high-performance embedded processing solutions, which allow you to

extend your product's life cycle and improve time to market over

standard product solutions.

Low-Cost DSP Solutions

Use Cyclone II FPGAs alone or as DSP co-processors to improve

price-to-performance ratios for digital signal processing (DSP)

applications. You can implement high-performance yet low-cost DSP

systems with the following Cyclone II features and design support:

■ Up to 150 18 × 18 multipliers

■ Up to 1.1 Mbit of on-chip embedded memory

■ High-speed interfaces to external memory

■ DSP intellectual property (IP) cores

■ DSP Builder interface to The Mathworks Simulink and Matlab

design environment

■ DSP Development Kit, Cyclone II Edition

Cyclone II devices include a powerful FPGA feature set optimized for

low-cost applications including a wide range of density, memory,

embedded multiplier, and packaging options. Cyclone II devices

 support a wide range of common external memory interfaces and 

I/O protocols required in low-cost applications. Parameterizable IP cores 

from Altera and partners make using Cyclone II interfaces and protocols fast and easy

Features

The Cyclone II device family offers the following features:

■ High-density architecture with 4,608 to 68,416 LEs

● M4K embedded memory blocks

● Up to 1.1 Mbits of RAM available without reducing available

logic

● 4,096 memory bits per block (4,608 bits per block including 512

parity bits)

● Variable port configurations of ×1, ×2, ×4, ×8, ×9, ×16, ×18, ×32,

and ×36

● True dual-port (one read and one write, two reads, or two

writes) operation for ×1, ×2, ×4, ×8, ×9, ×16, and ×18 modes

● Byte enables for data input masking during writes

● Up to 260-MHz operation

■ Embedded multipliers

● Up to 150 18- × 18-bit multipliers are each configurable as two

independent 9- × 9-bit multipliers with up to 250-MHz

performance

● Optional input and output registers

■ Advanced I/O support

● High-speed differential I/O standard support, including LVDS,

RSDS, mini-LVDS, LVPECL, differential HSTL, and differential

SSTL

● Single-ended I/O standard support, including 2.5-V and 1.8-V,

SSTL class I and II, 1.8-V and 1.5-V HSTL class I and II, 3.3-V PCI

and PCI-X 1.0, 3.3-, 2.5-, 1.8-, and 1.5-V LVCMOS, and 3.3-, 2.5-,

and 1.8-V LVTTL

● Peripheral Component Interconnect Special Interest Group (PCI

SIG) PCI Local Bus Specification, Revision 3.0 compliance for 3.3-V

operation at 33 or 66 MHz for 32- or 64-bit interfaces

● PCI Express with an external TI PHY and an Altera PCI Express

×1 Megacore® function

● 133-MHz PCI-X 1.0 specification compatibility

● High-speed external memory support, including DDR, DDR2,

and SDR SDRAM, and QDRII SRAM supported by drop in

Altera IP MegaCore functions for ease of use

● Three dedicated registers per I/O element (IOE): one input

register, one output register, and one output-enable register

● Programmable bus-hold feature

● Programmable output drive strength feature

● Programmable delays from the pin to the IOE or logic array

● I/O bank grouping for unique VCCIO and/or VREF bank

settings

● MultiVolt™ I/O standard support for 1.5-, 1.8-, 2.5-, and

3.3-interfaces

● Hot-socketing operation support

● Tri-state with weak pull-up on I/O pins before and during

configuration

● Programmable open-drain outputs

● Series on-chip termination support

■ Flexible clock management circuitry

● Hierarchical clock network for up to 402.5-MHz performance

● Up to four PLLs per device provide clock multiplication and

division, phase shifting, programmable duty cycle, and external

clock outputs, allowing system-level clock management and

skew control

● Up to 16 global clock lines in the global clock network that drive

throughout the entire device

■ Device configuration

● Fast serial configuration allows configuration times less than

100 ms

● Decompression feature allows for smaller programming file

storage and faster configuration times

● Supports multiple configuration modes: active serial, passive

serial, and JTAG-based configuration

● Supports configuration through low-cost serial configuration

devices

● Device configuration supports multiple voltages (either 3.3, 2.5,

or 1.8 V)

■ Intellectual property

● Altera megafunction and Altera MegaCore function support,

and Altera Megafunctions Partners Program (AMPPSM)

megafunction support, for a wide range of embedded

processors, on-chip and off-chip interfaces, peripheral

functions, DSP functions, and communications functions and 

protocols. Visit the Altera IPMegaStore at www.altera.com to

download IP MegaCore functions.

● Nios II Embedded Processor support

The Cyclone II family offers devices with the Fast-On feature, which

offers a faster power-on-reset (POR) time. Devices that support the

Fast-On feature are designated with an “A” in the device ordering code.For example, 

EP2C5A, EP2C8A, EP2C15A, and EP2C20A. The EP2C5A is only available in the automotive speed grade. 

The EP2C8A and EP2C20A are only available in the industrial speed grade. 

The EP2C15A is only available with the Fast-On feature and is available in both commercial and industrial grades. 

The Cyclone II “A” devices are identical in feature set and functionality to the non-A devices except for support of the faster POR time.

Cyclone II A devices are offered in automotive speed grade. For more

information, refer to the Cyclone II section in the Automotive-Grade Device Handbook.

For more information on POR time specifications for Cyclone II A and

non-A devices, refer to the Hot Socketing & Power-On Reset chapter in the Cyclone II Device Handbook.

Table 1–1 lists the Cyclone II device family features. Table 1–2 lists the

Cyclone II device package offerings and maximum user I/O pins.

How to choose FPGA for your project?

PDF