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Manufacturers
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Dual ARM® Cortex®-A9 MPCore™ with CoreSight™ System On Chip (SOC) IC Arria V ST FPGA - 462K Logic Elements 1.05GHz 1517-FBGA, FC (40x40)
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1950
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1517-BBGA, FCBGA
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Dual ARM® Cortex®-A9 MPCore™ with CoreSight™ System On Chip (SOC) IC Arria V SX FPGA - 350K Logic Elements 1.05GHz 1517-FBGA, FC (40x40)
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6297
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1517-BBGA, FCBGA
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System On Chip (SOC) IC *
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2192
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Arria II GX Field Programmable Gate Array (FPGA) IC 156 5371904 60214 358-LFBGA, FCBGA
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3593
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358-LFBGA, FCBGA
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Dual ARM® Cortex®-A9 MPCore™ with CoreSight™ System On Chip (SOC) IC Arria V SX FPGA - 462K Logic Elements 700MHz 1152-FBGA, FC (35x35)
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5518
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1152-BBGA, FCBGA
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Dual ARM® Cortex®-A9 MPCore™ with CoreSight™ System On Chip (SOC) IC Arria V SX FPGA - 462K Logic Elements 925MHz 896-FBGA (31x31)
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6837
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896-BBGA, FCBGA
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Quad ARM® Cortex®-A53 MPCore™ with CoreSight™, ARM NEON, Floating point System On Chip (SOC) IC Agilex F FPGA - 2.3M Logic Elements 1.4GHz 2340-BGA (45x42)
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1524
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2340-BFBGA Exposed Pad
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Arria II GX Field Programmable Gate Array (FPGA) IC 452 6839296 89178 1152-BBGA, FCBGA
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7415
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1152-BBGA, FCBGA
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Dual ARM® Cortex®-A9 MPCore™ with CoreSight™ System On Chip (SOC) IC Arria V SX FPGA - 462K Logic Elements 700MHz 1152-FBGA, FC (35x35)
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8469
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1152-BBGA, FCBGA
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Stratix® V GS Field Programmable Gate Array (FPGA) IC 696 46080000 583000 1517-BBGA, FCBGA
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6756
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1517-BBGA, FCBGA
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Cyclone® Field Programmable Gate Array (FPGA) IC 301 78336 4000 400-BGA Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR) interface to meet DDR SDRAM and fast cycle RAM (FCRAM) memory requirements, Cyclone devices are a cost-effective solution for data-path applications. Cyclone devices support various I/O standards, including LVDS at data rates up to 640 megabits per second (Mbps), and 66- and 33-MHz, 64- and 32-bit peripheral component interconnect (PCI), for interfacing with and supporting ASSP and ASIC devices. Altera also offers new low-cost serial configuration devices to configure Cyclone devices. Features The Cyclone device family offers the following features: ■ 2,910 to 20,060 LEs, see Table 1–1 ■ Up to 294,912 RAM bits (36,864 bytes) ■ Supports configuration through low-cost serial configuration device ■ Support for LVTTL, LVCMOS, SSTL-2, and SSTL-3 I/O standards ■ Support for 66- and 33-MHz, 64- and 32-bit PCI standard ■ High-speed (640 Mbps) LVDS I/O support ■ Low-speed (311 Mbps) LVDS I/O support ■ 311-Mbps RSDS I/O support ■ Up to two PLLs per device provide clock multiplication and phase shifting ■ Up to eight global clock lines with six clock resources available per logic array block (LAB) row ■ Support for external memory, including DDR SDRAM (133 MHz), FCRAM, and single data rate (SDR) SDRAM ■ Support for multiple intellectual property (IP) cores, including Altera® MegaCore® functions and Altera Megafunctions Partners Program (AMPPSM) megafunctions. |
2974
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400-BGA
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Arria II GX Field Programmable Gate Array (FPGA) IC 612 10177536 181165 1152-BBGA, FCBGA
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8518
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1152-BBGA, FCBGA
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Dual ARM® Cortex®-A9 MPCore™ with CoreSight™ System On Chip (SOC) IC Arria V SX FPGA - 462K Logic Elements 700MHz 896-FBGA, FC (31x31)
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5170
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896-BBGA, FCBGA
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Stratix® V GS Field Programmable Gate Array (FPGA) IC 432 13312000 236000 1152-BBGA, FCBGA
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9193
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1152-BBGA, FCBGA
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Cyclone® Field Programmable Gate Array (FPGA) IC 249 239616 12060 324-BGA Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR) interface to meet DDR SDRAM and fast cycle RAM (FCRAM) memory requirements, Cyclone devices are a cost-effective solution for data-path applications. Cyclone devices support various I/O standards, including LVDS at data rates up to 640 megabits per second (Mbps), and 66- and 33-MHz, 64- and 32-bit peripheral component interconnect (PCI), for interfacing with and supporting ASSP and ASIC devices. Altera also offers new low-cost serial configuration devices to configure Cyclone devices. Features The Cyclone device family offers the following features: ■ 2,910 to 20,060 LEs, see Table 1–1 ■ Up to 294,912 RAM bits (36,864 bytes) ■ Supports configuration through low-cost serial configuration device ■ Support for LVTTL, LVCMOS, SSTL-2, and SSTL-3 I/O standards ■ Support for 66- and 33-MHz, 64- and 32-bit PCI standard ■ High-speed (640 Mbps) LVDS I/O support ■ Low-speed (311 Mbps) LVDS I/O support ■ 311-Mbps RSDS I/O support ■ Up to two PLLs per device provide clock multiplication and phase shifting ■ Up to eight global clock lines with six clock resources available per logic array block (LAB) row ■ Support for external memory, including DDR SDRAM (133 MHz), FCRAM, and single data rate (SDR) SDRAM ■ Support for multiple intellectual property (IP) cores, including Altera® MegaCore® functions and Altera Megafunctions Partners Program (AMPPSM) megafunctions. Chip Altera Cyclone naming rules，Chinese chip Will replace it |
9858
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324-BGA
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Arria II GX Field Programmable Gate Array (FPGA) IC 252 3517440 42959 572-BGA, FCBGA
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1253
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572-BGA, FCBGA
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Dual ARM® Cortex®-A9 MPCore™ with CoreSight™ System On Chip (SOC) IC Arria V SX FPGA - 350K Logic Elements 800MHz 1517-FBGA, FC (40x40)
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7581
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1517-BBGA, FCBGA
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Stratix® V GX Field Programmable Gate Array (FPGA) IC 696 53248000 840000 1517-BBGA, FCBGA
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7537
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1517-BBGA, FCBGA
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Cyclone® Field Programmable Gate Array (FPGA) IC 104 59904 2910 144-LQFP Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR) interface to meet DDR SDRAM and fast cycle RAM (FCRAM) memory requirements, Cyclone devices are a cost-effective solution for data-path applications. Cyclone devices support various I/O standards, including LVDS at data rates up to 640 megabits per second (Mbps), and 66- and 33-MHz, 64- and 32-bit peripheral component interconnect (PCI), for interfacing with and supporting ASSP and ASIC devices. Altera also offers new low-cost serial configuration devices to configure Cyclone devices. Features The Cyclone device family offers the following features: ■ 2,910 to 20,060 LEs, see Table 1–1 ■ Up to 294,912 RAM bits (36,864 bytes) ■ Supports configuration through low-cost serial configuration device ■ Support for LVTTL, LVCMOS, SSTL-2, and SSTL-3 I/O standards ■ Support for 66- and 33-MHz, 64- and 32-bit PCI standard ■ High-speed (640 Mbps) LVDS I/O support ■ Low-speed (311 Mbps) LVDS I/O support ■ 311-Mbps RSDS I/O support ■ Up to two PLLs per device provide clock multiplication and phase shifting ■ Up to eight global clock lines with six clock resources available per logic array block (LAB) row ■ Support for external memory, including DDR SDRAM (133 MHz), FCRAM, and single data rate (SDR) SDRAM ■ Support for multiple intellectual property (IP) cores, including Altera® MegaCore® functions and Altera Megafunctions Partners Program (AMPPSM) megafunctions. Chip Altera Cyclone naming rules，Chinese chip Will replace it |
2777
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144-LQFP
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Arria II GX Field Programmable Gate Array (FPGA) IC 252 5371904 60214 572-BGA, FCBGA
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6536
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572-BGA, FCBGA
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Dual ARM® Cortex®-A9 MPCore™ with CoreSight™ System On Chip (SOC) IC Arria 10 SX FPGA - 660K Logic Elements 1.5GHz 1152-FBGA, FC (35x35)
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8279
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1152-BBGA, FCBGA
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Stratix® V GS Field Programmable Gate Array (FPGA) IC 840 51200000 695000 1932-BBGA, FCBGA
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4285
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1932-BBGA, FCBGA
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Cyclone® Field Programmable Gate Array (FPGA) IC 185 239616 12060 256-BGA Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR) interface to meet DDR SDRAM and fast cycle RAM (FCRAM) memory requirements, Cyclone devices are a cost-effective solution for data-path applications. Cyclone devices support various I/O standards, including LVDS at data rates up to 640 megabits per second (Mbps), and 66- and 33-MHz, 64- and 32-bit peripheral component interconnect (PCI), for interfacing with and supporting ASSP and ASIC devices. Altera also offers new low-cost serial configuration devices to configure Cyclone devices. Features The Cyclone device family offers the following features: ■ 2,910 to 20,060 LEs, see Table 1–1 ■ Up to 294,912 RAM bits (36,864 bytes) ■ Supports configuration through low-cost serial configuration device ■ Support for LVTTL, LVCMOS, SSTL-2, and SSTL-3 I/O standards ■ Support for 66- and 33-MHz, 64- and 32-bit PCI standard ■ High-speed (640 Mbps) LVDS I/O support ■ Low-speed (311 Mbps) LVDS I/O support ■ 311-Mbps RSDS I/O support ■ Up to two PLLs per device provide clock multiplication and phase shifting ■ Up to eight global clock lines with six clock resources available per logic array block (LAB) row ■ Support for external memory, including DDR SDRAM (133 MHz), FCRAM, and single data rate (SDR) SDRAM ■ Support for multiple intellectual property (IP) cores, including Altera® MegaCore® functions and Altera Megafunctions Partners Program (AMPPSM) megafunctions. Chip Altera Cyclone naming rules，Chinese chip Will replace it |
7808
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256-BGA
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Arria II GX Field Programmable Gate Array (FPGA) IC 372 6839296 89178 780-BBGA, FCBGA
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8881
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780-BBGA, FCBGA
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Arria 10 GX Field Programmable Gate Array (FPGA) IC 600 68857856 1150000 1517-BBGA, FCBGA
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9495
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1517-BBGA, FCBGA
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Stratix® V GS Field Programmable Gate Array (FPGA) IC 696 51200000 695000 1517-BBGA, FCBGA
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3096
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1517-BBGA, FCBGA
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Cyclone® Field Programmable Gate Array (FPGA) IC 249 78336 4000 324-BGA Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR) interface to meet DDR SDRAM and fast cycle RAM (FCRAM) memory requirements, Cyclone devices are a cost-effective solution for data-path applications. Cyclone devices support various I/O standards, including LVDS at data rates up to 640 megabits per second (Mbps), and 66- and 33-MHz, 64- and 32-bit peripheral component interconnect (PCI), for interfacing with and supporting ASSP and ASIC devices. Altera also offers new low-cost serial configuration devices to configure Cyclone devices. Features The Cyclone device family offers the following features: ■ 2,910 to 20,060 LEs, see Table 1–1 ■ Up to 294,912 RAM bits (36,864 bytes) ■ Supports configuration through low-cost serial configuration device ■ Support for LVTTL, LVCMOS, SSTL-2, and SSTL-3 I/O standards ■ Support for 66- and 33-MHz, 64- and 32-bit PCI standard ■ High-speed (640 Mbps) LVDS I/O support ■ Low-speed (311 Mbps) LVDS I/O support ■ 311-Mbps RSDS I/O support ■ Up to two PLLs per device provide clock multiplication and phase shifting ■ Up to eight global clock lines with six clock resources available per logic array block (LAB) row ■ Support for external memory, including DDR SDRAM (133 MHz), FCRAM, and single data rate (SDR) SDRAM ■ Support for multiple intellectual property (IP) cores, including Altera® MegaCore® functions and Altera Megafunctions Partners Program (AMPPSM) megafunctions. Chip Altera Cyclone naming rules，Chinese chip Will replace it |
4097
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324-BGA
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Arria II GX Field Programmable Gate Array (FPGA) IC 452 8315904 118143 1152-BBGA, FCBGA
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3825
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1152-BBGA, FCBGA
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IC QUAD-SERIAL LOW VOLTAGE CONFI
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9901
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24-LBGA
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Stratix® V GX Field Programmable Gate Array (FPGA) IC 600 46080000 490000 1517-BBGA, FCBGA
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6614
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1517-BBGA, FCBGA
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