Intel

Cyclone® IV GX Field Programmable Gate Array (FPGA) IC 72 1105920 29440 169-LBGA

Introduction

The CycloneTM field programmable gate array family is based ona 1.5-V,

0.13-um, alayer copper SRAM process, with densities up to 20,060 logic

elements (LEs) and up to 288 Kbits of RAM. With features like phase-

locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

interface to meet DDR SDRAM and fast cycle RAM (FCRAM) memory

requirements, Cyclone devices are a cost effective solution for data-path

applications. Cyclone devices support various I/O standards, including

LVDS at data rates up to 311 megabits per second (Mbps) and 66-MHz,

32-bit peripheral component interconnect (PCI), for interfacing with and

supporting ASSP and ASIC devices. Altera also offers new low-cost serial

configuration devices to configure Cyclone devices.

Features

■Up to 294,912 RAM bits (36,864 bytes)

■Supports configuration through low-cost serial configuration device

■Support for LVTTL, LVCMOS, SSTL-2, and SSTL-3 I/O standards

■Support for 66-MHz, 32-bit PCI standard

■Low speed (311 Mbps) LVDS 1/O support

■Up to two PLLs per device provide clock multiplication and phase shifting

■Up to eight global clock lines with six clock resources available per

logic array block (LAB) row

■Support for external memory, induding DDR SDRAM (133 MHz),

FCRAM, and single data rate (SDR) SDRAM

■Support for multiple intellectual property (IP) cores, including

Altera" MegaCore functions and Altera Megafunctions Partners

Program (AMPPSM) megafunctions

Chip Altera Cyclone naming rules，Chinese chip Will replace it

PDF

Cyclone® V E Field Programmable Gate Array (FPGA) IC 176 2002944 25000 324-LFBGA

Summary of Features for Cyclone V Devices

Technology

• TSMC's 28-nm low-power (28LP) process technology

• 1.1 V core voltage

Packaging

• Wirebond low-halogen packages

• Multiple device densities with compatible package footprints for seamless migration between

different device densities

• RoHS-compliant and leaded(1)options

High-performance FPGA fabric

Enhanced 8-input ALM with four registers

Internal memory blocks

• M10K—10-kilobits (Kb) memory blocks with soft error correction code (ECC)

• Memory logic array block (MLAB)—640-bit distributed LUTRAM where you can use up to 25%

of the ALMs as MLAB memory

Embedded Hard IP blocks

Variable-precision DSP

• Native support for up to three signal processing precision levels

(three 9 x 9, two 18 x 18, or one 27 x 27 multiplier) in the same

variable-precision DSP block

• 64-bit accumulator and cascade

• Embedded internal coefficient memory

• Preadder/subtractor for improved efficiency

Memory controller

DDR3, DDR2, and LPDDR2 with 16 and 32 bit ECC support

Embedded transceiver I/O

PCI Express* (PCIe*) Gen2 and Gen1 (x1, x2, or x4) hard IP with

multifunction support, endpoint, and root port

Clock networks

• Up to 550 MHz global clock network

• Global, quadrant, and peripheral clock networks

• Clock networks that are not used can be powered down to reduce dynamic power

Phase-locked loops (PLLs)

• Precision clock synthesis, clock delay compensation, and zero delay buffering (ZDB)

• Integer mode and fractional mode

FPGA General-purpose I/Os (GPIOs)

• 875 megabits per second (Mbps) LVDS receiver and 840 Mbps LVDS transmitter

• 400 MHz/800 Mbps external memory interface

• On-chip termination (OCT)

• 3.3 V support with up to 16 mA drive strength

Low-power high-speed serial interface

• 614 Mbps to 6.144 Gbps integrated transceiver speed

• Transmit pre-emphasis and receiver equalization

• Dynamic partial reconfiguration of individual channels

HPS(Cyclone V SE, SX,and ST devices only)

• Single or dual-core Arm Cortex-A9 MPCore processor-up to 925 MHz maximum frequency with

support for symmetric and asymmetric multiprocessing

• Interface peripherals—10/100/1000 Ethernet media access control (EMAC), USB 2.0

On-The-GO (OTG) controller, quad serial peripheral interface (QSPI) flash controller, NAND

flash controller, Secure Digital/MultiMediaCard (SD/MMC) controller, UART, controller area

network (CAN), serial peripheral interface (SPI), I2C interface, and up to 85 HPS GPIO

interfaces

• System peripherals—general-purpose timers, watchdog timers, direct memory access (DMA)

controller, FPGA configuration manager, and clock and reset managers

• On-chip RAM and boot ROM

• HPS–FPGA bridges—include the FPGA-to-HPS, HPS-to-FPGA, and lightweight HPS-to-FPGA

bridges that allow the FPGA fabric to issue transactions to slaves in the HPS, and vice versa

• FPGA-to-HPS SDRAM controller subsystem—provides a configurable interface to the multiport

front end (MPFE) of the HPS SDRAM controller

• Arm CoreSight™ JTAG debug access port, trace port, and on-chip trace storage

Configuration

• Tamper protection—comprehensive design protection to protect your valuable IP investments

• Enhanced advanced encryption standard (AES) design security features

• CvP

• Dynamic reconfiguration of the FPGA

• Active serial (AS) x1 and x4, passive serial (PS), JTAG, and fast passive parallel (FPP) x8 and

x16 configuration options

• Internal scrubbing (2)

• Partial reconfiguration (3)

How to choose FPGA for your project?

PDF

Cyclone® V E Field Programmable Gate Array (FPGA) IC 224 14251008 301000 484-BGA

Summary of Features for Cyclone V Devices

Technology

• TSMC's 28-nm low-power (28LP) process technology

• 1.1 V core voltage

Packaging

• Wirebond low-halogen packages

• Multiple device densities with compatible package footprints for seamless migration between

different device densities

• RoHS-compliant and leaded(1)options

High-performance FPGA fabric

Enhanced 8-input ALM with four registers

Internal memory blocks

• M10K—10-kilobits (Kb) memory blocks with soft error correction code (ECC)

• Memory logic array block (MLAB)—640-bit distributed LUTRAM where you can use up to 25%

of the ALMs as MLAB memory

Embedded Hard IP blocks

Variable-precision DSP

• Native support for up to three signal processing precision levels

(three 9 x 9, two 18 x 18, or one 27 x 27 multiplier) in the same

variable-precision DSP block

• 64-bit accumulator and cascade

• Embedded internal coefficient memory

• Preadder/subtractor for improved efficiency

Memory controller

DDR3, DDR2, and LPDDR2 with 16 and 32 bit ECC support

Embedded transceiver I/O

PCI Express* (PCIe*) Gen2 and Gen1 (x1, x2, or x4) hard IP with

multifunction support, endpoint, and root port

Clock networks

• Up to 550 MHz global clock network

• Global, quadrant, and peripheral clock networks

• Clock networks that are not used can be powered down to reduce dynamic power

Phase-locked loops (PLLs)

• Precision clock synthesis, clock delay compensation, and zero delay buffering (ZDB)

• Integer mode and fractional mode

FPGA General-purpose I/Os (GPIOs)

• 875 megabits per second (Mbps) LVDS receiver and 840 Mbps LVDS transmitter

• 400 MHz/800 Mbps external memory interface

• On-chip termination (OCT)

• 3.3 V support with up to 16 mA drive strength

Low-power high-speed serial interface

• 614 Mbps to 6.144 Gbps integrated transceiver speed

• Transmit pre-emphasis and receiver equalization

• Dynamic partial reconfiguration of individual channels

HPS(Cyclone V SE, SX,and ST devices only)

• Single or dual-core Arm Cortex-A9 MPCore processor-up to 925 MHz maximum frequency with

support for symmetric and asymmetric multiprocessing

• Interface peripherals—10/100/1000 Ethernet media access control (EMAC), USB 2.0

On-The-GO (OTG) controller, quad serial peripheral interface (QSPI) flash controller, NAND

flash controller, Secure Digital/MultiMediaCard (SD/MMC) controller, UART, controller area

network (CAN), serial peripheral interface (SPI), I2C interface, and up to 85 HPS GPIO

interfaces

• System peripherals—general-purpose timers, watchdog timers, direct memory access (DMA)

controller, FPGA configuration manager, and clock and reset managers

• On-chip RAM and boot ROM

• HPS–FPGA bridges—include the FPGA-to-HPS, HPS-to-FPGA, and lightweight HPS-to-FPGA

bridges that allow the FPGA fabric to issue transactions to slaves in the HPS, and vice versa

• FPGA-to-HPS SDRAM controller subsystem—provides a configurable interface to the multiport

front end (MPFE) of the HPS SDRAM controller

• Arm CoreSight™ JTAG debug access port, trace port, and on-chip trace storage

Configuration

• Tamper protection—comprehensive design protection to protect your valuable IP investments

• Enhanced advanced encryption standard (AES) design security features

• CvP

• Dynamic reconfiguration of the FPGA

• Active serial (AS) x1 and x4, passive serial (PS), JTAG, and fast passive parallel (FPP) x8 and

x16 configuration options

• Internal scrubbing (2)

• Partial reconfiguration (3)

MAX® 10 Field Programmable Gate Array (FPGA) IC 130 387072 8000 169-LFBGA

Intel® MAX® 10 FPGA Device Overview

Intel® MAX® 10 devices are single-chip, non-volatile low-cost programmable logic

devices (PLDs) to integrate the optimal set of system components.

The highlights of the Intel MAX 10 devices include:

• Internally stored dual configuration flash

• User flash memory

• Instant on support

• Integrated analog-to-digital converters (ADCs)

• Single-chip Nios II soft core processor support

Intel MAX 10 devices are the ideal solution for system management, I/O expansion,

communication control planes, industrial, automotive, and consumer applications.

Supporting Feature

Secure on-die flash memory enables device configuration in less than 10 ms

• Single device integrating PLD logic, RAM, flash memory, digital signal processing (DSP), ADC, phase-locked loop (PLL), and I/Os

• Small packages available from 3 mm × 3 mm

• Sleep mode—significant standby power reduction and resumption in less than 1 ms

• Longer battery life—resumption from full power-off in less than 10 ms

Built on TSMC's 55 nm embedded flash process technology

• Intel Quartus® Prime Lite edition (no cost license)

• Platform Designer (Standard) system integration tool

• DSP Builder for Intel FPGAs

• Nios® II Embedded Design Suite (EDS)

How to choose FPGA for your project?

MAX® 10 Field Programmable Gate Array (FPGA) IC 101 387072 8000 144-LQFP Exposed Pad

Intel® MAX® 10 FPGA Device Overview

Intel® MAX® 10 devices are single-chip, non-volatile low-cost programmable logic

devices (PLDs) to integrate the optimal set of system components.

The highlights of the Intel MAX 10 devices include:

• Internally stored dual configuration flash

• User flash memory

• Instant on support

• Integrated analog-to-digital converters (ADCs)

• Single-chip Nios II soft core processor support

Intel MAX 10 devices are the ideal solution for system management, I/O expansion,

communication control planes, industrial, automotive, and consumer applications.

Feature

Technology

55 nm TSMC Embedded Flash (Flash + SRAM) process technology

Packaging

• Low cost, small form factor packages—support multiple packaging technologies and pin pitches

• Multiple device densities with compatible package footprints for seamless migration between different device densities

• RoHS6-compliant

Core architecture

• 4-input look-up table (LUT) and single register logic element (LE)

• LEs arranged in logic array block (LAB)

• Embedded RAM and user flash memory

• Clocks and PLLs

• Embedded multiplier blocks

• General purpose I/Os

Internal memory blocks

• M9K—9 kilobits (Kb) memory blocks

• Cascadable blocks to create RAM, dual port, and FIFO functions

User flash memory (UFM)

• User accessible non-volatile storage

• High speed operating frequency

• Large memory size

• High data retention

• Multiple interface option

Embedded multiplier blocks

• One 18 × 18 or two 9 × 9 multiplier modes

• Cascadable blocks enabling creation of filters, arithmetic functions, and image processing pipelines

ADC

• 12-bit successive approximation register (SAR) type

• Up to 17 analog inputs

• Cumulative speed up to 1 million samples per second ( MSPS)

• Integrated temperature sensing capability

Clock networks

• Global clocks support

• High speed frequency in clock network

Internal oscillator

Built-in internal ring oscillator

PLLs

• Analog-based

• Low jitter

• High precision clock synthesis

• Clock delay compensation

• Zero delay buffering

• Multiple output taps

General-purpose I/Os (GPIOs)

• Multiple I/O standards support

• On-chip termination (OCT)

• Up to 830 megabits per second (Mbps) LVDS receiver, 800 Mbps LVDS transmitter

External memory interface (EMIF) (1)

Supports up to 600 Mbps external memory interfaces:

How to choose FPGA for your project?

Cyclone® V GT Field Programmable Gate Array (FPGA) IC 240 14251008 301000 484-FBGA

Summary of Features for Cyclone V Devices

Technology

• TSMC's 28-nm low-power (28LP) process technology

• 1.1 V core voltage

Packaging

• Wirebond low-halogen packages

• Multiple device densities with compatible package footprints for seamless migration between

different device densities

• RoHS-compliant and leaded(1)options

High-performance FPGA fabric

Enhanced 8-input ALM with four registers

Internal memory blocks

• M10K—10-kilobits (Kb) memory blocks with soft error correction code (ECC)

• Memory logic array block (MLAB)—640-bit distributed LUTRAM where you can use up to 25%

of the ALMs as MLAB memory

Embedded Hard IP blocks

Variable-precision DSP

• Native support for up to three signal processing precision levels

(three 9 x 9, two 18 x 18, or one 27 x 27 multiplier) in the same

variable-precision DSP block

• 64-bit accumulator and cascade

• Embedded internal coefficient memory

• Preadder/subtractor for improved efficiency

Memory controller

DDR3, DDR2, and LPDDR2 with 16 and 32 bit ECC support

Embedded transceiver I/O

PCI Express* (PCIe*) Gen2 and Gen1 (x1, x2, or x4) hard IP with

multifunction support, endpoint, and root port

Clock networks

• Up to 550 MHz global clock network

• Global, quadrant, and peripheral clock networks

• Clock networks that are not used can be powered down to reduce dynamic power

Phase-locked loops (PLLs)

• Precision clock synthesis, clock delay compensation, and zero delay buffering (ZDB)

• Integer mode and fractional mode

FPGA General-purpose I/Os (GPIOs)

• 875 megabits per second (Mbps) LVDS receiver and 840 Mbps LVDS transmitter

• 400 MHz/800 Mbps external memory interface

• On-chip termination (OCT)

• 3.3 V support with up to 16 mA drive strength

Low-power high-speed serial interface

• 614 Mbps to 6.144 Gbps integrated transceiver speed

• Transmit pre-emphasis and receiver equalization

• Dynamic partial reconfiguration of individual channels

HPS(Cyclone V SE, SX,and ST devices only)

• Single or dual-core Arm Cortex-A9 MPCore processor-up to 925 MHz maximum frequency with

support for symmetric and asymmetric multiprocessing

• Interface peripherals—10/100/1000 Ethernet media access control (EMAC), USB 2.0

On-The-GO (OTG) controller, quad serial peripheral interface (QSPI) flash controller, NAND

flash controller, Secure Digital/MultiMediaCard (SD/MMC) controller, UART, controller area

network (CAN), serial peripheral interface (SPI), I2C interface, and up to 85 HPS GPIO

interfaces

• System peripherals—general-purpose timers, watchdog timers, direct memory access (DMA)

controller, FPGA configuration manager, and clock and reset managers

• On-chip RAM and boot ROM

• HPS–FPGA bridges—include the FPGA-to-HPS, HPS-to-FPGA, and lightweight HPS-to-FPGA

bridges that allow the FPGA fabric to issue transactions to slaves in the HPS, and vice versa

• FPGA-to-HPS SDRAM controller subsystem—provides a configurable interface to the multiport

front end (MPFE) of the HPS SDRAM controller

• Arm CoreSight™ JTAG debug access port, trace port, and on-chip trace storage

Configuration

• Tamper protection—comprehensive design protection to protect your valuable IP investments

• Enhanced advanced encryption standard (AES) design security features

• CvP

• Dynamic reconfiguration of the FPGA

• Active serial (AS) x1 and x4, passive serial (PS), JTAG, and fast passive parallel (FPP) x8 and

x16 configuration options

• Internal scrubbing (2)

• Partial reconfiguration (3)

MAX® 10 Field Programmable Gate Array (FPGA) IC 101 562176 16000 144-LQFP Exposed Pad

Intel® MAX® 10 FPGA Device Datasheet

This datasheet describes the electrical characteristics, switching characteristics, configuration specifications, and timing for

Intel MAX® 10 devices.

Intel MAX 10 Device Grades and Speed Grades Supported

Commercial

• –C7

• –C8 (slowest)

Industrial

• –I6 (fastest)

• –I7

Automotive

• –A6

• –A7