Lattice Semiconductor Corporation

MachXO3 Field Programmable Gate Array (FPGA) IC 206 245760 6864 256-LFBGA

General Description

MachXO3™ device family is an Ultra-Low Density family that supports the most advanced programmable bridging and

I/O expansion. It has the breakthrough I/O density and the lowest cost per I/O. The device I/O features have the

integrated support for latest industry standard I/O.

The MachXO3L/LF family of low power, instant-on, non-volatile PLDs has five devices with densities ranging from 640 to

9400 Look-Up Tables (LUTs). In addition to LUT-based, low-cost programmable logic these devices feature Embedded

Block RAM (EBR), Distributed RAM, Phase Locked Loops (PLLs), pre-engineered source synchronous I/O support, advanced

configuration support including dual-boot capability and hardened versions of commonly used functions such as SPI

controller, I2C controller and timer/counter. MachXO3LF devices also support User Flash Memory (UFM). These features

allow these devices to be used in low cost, high volume applications such as consumer electronics, compute and storage,

wireless communications, industrial control, and automotive systems.

The MachXO3L/LF devices are designed on a 65 nm non-volatile low power process. The device architecture has several

features such as programmable low swing differential I/O and the ability to turn off I/O banks, on-chip PLLs and

oscillators dynamically. These features help manage static and dynamic power consumption resulting in low static power

for all members of the family.

The MachXO3L/LF devices are available in two versions C and E with two speed grades: -5 and -6, with -6 being the

fastest. C devices have an internal linear voltage regulator which supports external VCC supply voltages of 3.3 V or 2.5 V.

E devices only accept 1.2 V as the external VCC supply voltage. With the exception of power supply voltage both C and E

are functionally compatible with each other.

The MachXO3L/LF PLDs are available in a broad range of advanced halogen-free packages ranging from the space saving

2.5 x 2.5 mm WLCSP to the 19 x 19 mm caBGA. MachXO3L/LF devices support density migration within the same package.

Table 1.1 shows the LUT densities, package and I/O options, along with other key parameters.

The MachXO3L/LF devices offer enhanced I/O features  such as drive strength control, slew rate control, PCI compatibility,

bus-keeper latches, pull-up resistors, pull-down resistors, open drain outputs and hot socketing. Pull-up, pull-down and

bus-keeper features are controllable on a “per-pin” basis. A user-programmable internal oscillator is included in

MachXO3L/LF devices. The clock output from this oscillator may be divided by the timer/counter for use as clock input in

functions such as LED control, keyboard scanner and similar state machines.

The MachXO3L/LF devices also provide flexible, reliable and secure configuration from on-chip NVCM/Flash. These

devices can also configure themselves from external SPI Flash or be configured by an external master through the JTAG

test access port or through the I²C port. Additionally, MachXO3L/LF devices support dual-boot capability (using external

Flash memory) and remote field upgrade (TransFR) capability.

Lattice provides a variety of design tools that allow complex designs to be efficiently implemented using the

MachXO3L/LF family of devices. Popular logic synthesis tools provide synthesis library support for MachXO3L/LF. Lattice

design tools use the synthesis tool output along with the user-specified preferences and constraints to place and route

the design in the MachXO3L/LF device. These tools extract the timing from the routing and back-annotate it into the

design for timing verification.

Lattice provides many pre-engineered IP (Intellectual Property) LatticeCORE™ modules, including a number of reference

designs licensed free of charge, optimized for the MachXO3L/LF PLD family. By using these configurable soft core IP

cores as standardized blocks, users are free to concentrate on the unique aspects of their design, increasing their

productivity.

Features

• Solutions

      Smallest footprint, lowest power, high data throughput bridging solutions for mobile applications

      Optimized footprint, logic density, I/O count, I/O performance devices for I/O management and logic applications

      High I/O logic, lowest cost I/O, high I/O devices for I/O expansion applications

• Flexible Architecture

      Logic Density ranging from 64 to 9.4 k LUT4

      High I/O to LUT ratio with up to 384 I/O pins

• Advanced Packaging

      0.4 mm pitch: 1 k to 4 k densities in very small footprint WLCSP (2.5 mm × 2.5 mm to 3.8 mm × 3.8 mm) with 28 to

      63 I/O

      0.5 mm pitch: 640 to 9.4 k LUT densities in 6 mm x 6 mm to 10 mm x 10 mm BGA packages with up to281 I/O

      0.8 mm pitch: 1 k to 9.4 k densities with up to 384 I/O in BGA packages

• Pre-Engineered Source Synchronous I/O

      DDR registers in I/O cells

      Dedicated gearing logic

      7:1 Gearing for Display I/O

      Generic DDR, DDRx2, DDRx4

• High Performance, Flexible I/O Buffer

      Programmable sysI/O™ buffer supports wide range of interfaces:

            LVCMOS 3.3/2.5/1.8/1.5/1.2

            LVTTL

            LVDS, Bus-LVDS, MLVDS, LVPECL

            MIPI D-PHY Emulated

            Schmitt trigger inputs, up to 0.5 V hysteresis

      Ideal for I/O bridging applications

      I/O support hot socketing

      On-chip differential termination

      Programmable pull-up or pull-down mode

• Flexible On-Chip Clocking

      Eight primary clocks

      Up to two edge clocks for high-speed I/O interfaces (top and bottom sides only)

      Up to two analog PLLs per device with fractional-n frequency synthesis

            Wide input frequency range (7 MHz to 400 MHz).

• Non-volatile, Multi-time Programmable

      Instant-on

            Powers up in microseconds

      Optional dual boot with external SPI memory

      Single-chip, secure solution

      Programmable through JTAG, SPI or I2C

      MachXO3L includes multi-time programmable NVCM

      MachXO3LF reconfigurable Flash includes 100,000 write/erase cycle for commercial/industrial devices and 10,000 for

      automotive devices

      Supports background programming of non volatile memory

• TransFR Reconfiguration

      In-field logic update while I/O holds the system state

• Enhanced System Level Support

      On-chip hardened functions: SPI, I2C, timer/counter

      On-chip oscillator with 5.5% accuracy for commercial/industrial devices

      Unique TraceID for system tracking

      Single power supply with extended operatingrange

      IEEE Standard 1149.1 boundary scan

      IEEE 1532 compliant in-system programming

• Applications

      Consumer Electronics

      Compute and Storage

      Wireless Communications

      Industrial Control Systems

      Automotive System

• Low Cost Migration Path

      Migration from the Flash based MachXO3LF to the NVCM based MachXO3L

      Pin compatible and equivalent timing

How to choose FPGA for your project?

PDF

CrossLink™ Field Programmable Gate Array (FPGA) IC 37 184320 5936 80-TFBGA

General Description

CrossLink™ from Lattice Semiconductor is a programmable video bridging device that supports a variety of protocols and

interfaces for mobile image sensors and displays. The device is based on Lattice mobile FPGA 40-nm technology. It

combines the extreme flexibility of an FPGA with the low power, low cost and small footprint of an ASIC.

CrossLink supports video interfaces including MIPI® DPI, MIPI DBI, CMOS camera and display interfaces, OpenLDI,

FPD-Link, FLATLINK, MIPI D-PHY, MIPI CSI-2, MIPI DSI, SLVS200, subLVDS, HiSPi and more.

Lattice Semiconductor provides many pre-engineered IP (Intellectual Property) modules for CrossLink. By using these

configurable soft core IPs as standardized blocks, designers are free to concentrate on the unique aspects of their design,

increasing their productivity.

The Lattice Diamond® design software allows large complex designs to be efficiently implemented using CrossLink.

Synthesis library support for CrossLink devices is available for popular logic synthesis tools. The Diamond tools use the

synthesis tool output along with the constraints from its floor planning tools to place and route the design in the

CrossLink device. The tools extract the timing from the routing and back-annotate it into the design for timing verification.

Interfaces on CrossLink provide a variety of bridging solutions for smart phone, tablets, wearables, VR, AR, Drone, Smart

Home, HMI as well as adjacent ISM markets. The device is capable of supporting high-resolution, high-bandwidth content

for mobile cameras and displays at 4 UHD and beyond.

Features

• Ultra-low power

• Sleep Mode Support

• Normal Operation – From 5 mW to 150 mW

• Ultra small footprint packages

      36-ball WLCSP (6 mm2)

      64-ball ucfBGA (12 mm2)

      80-ball ctfBGA (42 mm2)

      80-ball ckfBGA (49 mm2)

      81-ball csfBGA (20 mm2)

• Programmable architecture

      5936 LUTs

      180 Kb block RAM

      47 Kb distributed RAM

• Two hardened 4-lane MIPI D-PHY interfaces

      Transmit and receive

      6 Gb/s per D-PHY interface

• Programmable source synchronous I/O

      MIPI D-PHY Rx, LVDS Rx, LVDS Tx, subLVDS Rx, SLVS200 Rx, HiSPi Rx

      Up to 1200 Mb/s per I/O

      Four high-speed clock inputs

• Programmable CMOS I/O

      LVTTL and LVCMOS

      3.3 V, 2.5 V, 1.8 V and 1.2 V (outputs)

      LVCMOS differential outputs

• Flexible device configuration

      One Time Programmable (OTP) non-volatile configuration memory

      Master SPI boot from external flash

      Dual image booting supported

      I2C programming

      SPI programming

      TransFR™ I/O for simple field updates

• Enhanced system level support

      Reveal logic analyzer

      TraceID for system tracking

      On-chip hardened I2C block

• Applications examples

      Dual MIPI CSI-2 to Single MIPI CSI-2 Aggregation

      Quad MIPI CSI-2 to Single MIPI CSI-2 Aggregation

      Single MIPI DSI to Single MIPI DSI Repeater

      Single MIPI CSI-2 to Single MIPI CSI-2 Repeater

      Single MIPI DSI to Dual MIPI DSI Splitter

      Single MIPI CSI-2 to Dual MIPI CSI-2 Splitter

      MIPI DSI to OpenLDI/FPD-Link/LVDS Translator

      OpenLDI/FPD-Link/LVDS to MIPI DSI Translator

      MIPI DSI/CSI-2 to CMOS Translator

      CMOS to MIPI DSI/CSI-2 Translator

      subLVDS to MIPI CSI-2 Translator

How to choose FPGA for your project?

PDF

ECP5 Field Programmable Gate Array (FPGA) IC 197 589824 12000 256-LFBGA

General Description

The ECP5™/ECP5-5G™ family of FPGA devices is optimized to deliver high performance features such as an enhanced DSP

architecture, high speed SERDES (Serializer/Deserializer), and high speed source synchronous interfaces, in an economical

FPGA fabric. This combination is achieved through advances in device architecture and the use of 40 nm technology

making the devices suitable for high-volume, high-speed, and low-cost applications.

The ECP5/ECP5-5G device family covers look-up-table (LUT) capacity to 84K logic elements and supports up to 365 user

I/O. The ECP5/ECP5-5G device family also offers up to 156 18 x 18 multipliers and a wide range of parallel I/O standards.

The ECP5/ECP5-5G FPGA fabric is optimized high performance with low power and low cost in mind. The ECP5/ ECP5-5G

devices utilize reconfigurable SRAM logic technology and provide popular building blocks such as LUT-based logic,

distributed and embedded memory, Phase-Locked Loops (PLLs), Delay-Locked Loops (DLLs), pre-engineered source

synchronous I/O support, enhanced sysDSP slices and advanced configuration support, including encryption and dual-boot

capabilities.

The pre-engineered source synchronous logic implemented in the ECP5/ECP5-5G device family supports a broad range of

interface standards including DDR2/3, LPDDR2/3, XGMII, and 7:1 LVDS.

The ECP5/ECP5-5G device family also features high speed SERDES with dedicated Physical Coding Sublayer (PCS) functions.

High jitter tolerance and low transmit jitter allow the SERDES plus PCS blocks to be configured to support an array of

popular data protocols including PCI Express, Ethernet (XAUI, GbE, and SGMII) and CPRI. Transmit De-emphasis with

pre- and post-cursors, and Receive Equalization settings make the SERDES suitable for transmission and reception over

various forms of media.

The ECP5/ECP5-5G devices also provide flexible, reliable and secure configuration options, such as dual-boot capability,

bit-stream encryption, and TransFR field upgrade features.

ECP5-5G family devices have made some enhancement in the SERDES compared to ECP5UM devices. These enhancements

increase the performance of the SERDES to up to 5 Gb/s data rate.

The ECP5-5G family devices are pin-to-pin compatible with the ECP5UM devices. These allows a migration path for you to

port designs from ECP5UM to ECP5-5G devices to get higher performance.

The Lattice Diamond™ design software allows large complex designs to be efficiently implemented using the ECP5/ECP5-5G

FPGA family. Synthesis library support for ECP5/ECP5-5G devices is available for popular logic synthesis tools. The

Diamond tools use the synthesis tool output along with the constraints from its floor planning tools to place and route the

design in the ECP5/ECP5-5G device. The tools extract the timing from the routing and back-annotate it into the design for

timing verification.

Lattice provides many pre-engineered IP (Intellectual Property) modules for the ECP5/ECP5-5G family. Byusing these

configurable soft core IPs as standardized blocks, designers are free to concentrate on the unique aspects of their design,

increasing their productivity.

Features

• Higher Logic Density for Increased System Integration

      12K to 84K LUTs

      197 to 365 user programmable I/O

• Embedded SERDES

      270 Mb/s, up to 3.2 Gb/s, SERDES interface (ECP5)

      270 Mb/s, up to 5.0 Gb/s, SERDES interface (ECP5-5G)

      Supports eDP in RDR (1.62 Gb/s) and HDR

      (2.7 Gb/s)

      Up to four channels per device: PCI Express, Ethernet (1GbE, SGMII, XAUI), and CPRI

• sysDSP™

      Fully cascadable slice architecture

      12 to 160 slices for high performance multiply and accumulate

      Powerful 54-bit ALU operations

      Time Division Multiplexing MAC Sharing

      Rounding and truncation

      Each slice supports

            Half 36 x 36, two 18 x 18 or four 9 x 9 multipliers

            Advanced 18 x 36 MAC and 18 x 18 Multiply-Multiply-Accumulate (MMAC) operations

• Flexible Memory Resources

      Up to 3.744 Mb sysMEM™ Embedded Block

      RAM (EBR)

      194K to 669K bits distributed RAM

• sysCLOCK Analog PLLs and DLLs

      Four DLLs and four PLLs in LFE5-45 and LFE5-85; two DLLs and two PLLs in LFE5-25 and LFE5-12

• Pre-Engineered Source Synchronous I/O

      DDR registers in I/O cells

      Dedicated read/write levelling functionality

      Dedicated gearing logic

      Source synchronous standards support

      ADC/DAC, 7:1 LVDS, XGMII

      High Speed ADC/DAC devices

      Dedicated DDR2/DDR3 and LPDDR2/LPDDR3 memory support with DQS logic, up to 800 Mb/s data-rate

• Programmable sysI/O™ Buffer Supports Wide Range of Interfaces

      On-chip termination

      LVTTL and LVCMOS 33/25/18/15/12

      SSTL 18/15 I, II

      HSUL12

      LVDS, Bus-LVDS, LVPECL, RSDS, MLVDS

      subLVDS and SLVS, SoftIP MIPI D-PHY receiver/transmitter interfaces

• Flexible Device Configuration

      Shared bank for configuration I/O

      SPI boot flash interface

      Dual-boot images supported

      Slave SPI

      TransFR™ I/O for simple field updates

• Single Event Upset (SEU) Mitigation Support

      Soft Error Detect – Embedded hard macro

      Soft Error Correction – Without stopping user operation

      Soft Error Injection – Emulate SEU event to debug system error handling

• System Level Support

      IEEE 1149.1 and IEEE 1532 compliant

      Reveal Logic Analyzer

      On-chip oscillator for initialization and general use

      V core power supply for ECP5, 1.2 V core power supply for ECP5UM5G

How to choose FPGA for your project?

PDF