Lattice Semiconductor Corporation

iCE40™ LP Field Programmable Gate Array (FPGA) IC 21 384 32-VFQFN Exposed Pad

General Description

The iCE40 family of ultra-low power, non-volatile FPGAs has five devices with densities ranging from 384 to 7680Look-Up

Tables (LUTs). In addition to LUT-based, low-cost programmable logic, these devices feature EmbeddedBlock RAM (EBR),

Non-volatile Configuration Memory (NVCM) and Phase Locked Loops (PLLs). These featuresallow the devices to be used

in low-cost, high-volume consumer and system applications. Select packages offerHigh-Current drivers that are ideal to

drive three white LEDs, or one RGB LED.

The iCE40 devices are fabricated on a 40 nm CMOS low power process. The device architecture has several features such

as programmable low-swing differential I/Os and the ability to turn off on-chip PLLs dynamically. Thesefeatures help

manage static and dynamic power consumption, resulting in low static power for all members of thefamily. The iCE40

devices are available in two versions – ultra low power (LP) and high performance (HX) devices.

The iCE40 FPGAs are available in a broad range of advanced halogen-free packages ranging from the spacesaving

1.40x1.48 mm WLCSP to the PCB-friendly 20x20 mm TQFP. Table 1-1 shows the LUT densities, packageand I/O options,

along with other key parameters.

The iCE40 devices offer enhanced I/O features such as pull-up resistors. Pull-up features are controllable on a“per-pin”

basis.

The iCE40 devices also provide flexible, reliable and secure configuration from on-chip NVCM. These devices canalso

configure themselves from external SPI Flash or be configured by an external master such as a CPU.

Lattice provides a variety of design tools that allow complex designs to be efficiently implemented using the iCE40family

of devices. Popular logic synthesis tools provide synthesis library support for iCE40. Lattice design tools usethe synthesis

tool output along with the user-specified preferences and constraints to place and route the design inthe iCE40 device.

These tools extract the timing from the routing and back-annotate it into the design for timing ver-ification.

Lattice provides many pre-engineered IP (Intellectual Property) modules, including a number of reference designs,licensed

free of charge, optimized for the iCE40 FPGA family. By using these configurable soft core IP cores asstandardized blocks,

users are free to concentrate on the unique aspects of their design, increasing their productivity.

Features

• Flexible Logic Architecture

      Five devices with 384 to 7,680 LUT4s and10 to 206 I/Os

• Ultra Low Power Devices

      Advanced 40 nm low power process

      As low as 21 µA standby power

      Programmable low swing differential I/Os

• Embedded and Distributed Memory

      Up to 128 kbits sysMEM™ Embedded Block RAM

• Pre-Engineered Source Synchronous I/O

      DDR registers in I/O cells

• High Current LED Drivers

      Three High Current Drivers used for three differ-ent LEDs or one RGB LED

• High Performance, Flexible I/O Buffer

      Programmable sysIO™ buffer supports wide range of interfaces:

      — LVCMOS 3.3/2.5/1.8

      — LVDS25E, subLVDS

      — Schmitt trigger inputs, to 200 mV typical hysteresis

      Programmable pull-up mode

• Flexible On-Chip Clocking

      Eight low-skew global clock resources

      Up to two analog PLLs per device

• Flexible Device Configuration

      SRAM is configured through:

      — Standard SPI Interface

      — Internal Nonvolatile Configuration Memory (NVCM)

• Broad Range of Package Options

      WLCSP, QFN, VQFP, TQFP, ucBGA, caBGA, and csBGA package options

      Small footprint package options

      — As small as 1.40 mm x 1.48 mm

      Advanced halogen-free packaging

How to choose FPGA for your project?

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MachXO2 Field Programmable Gate Array (FPGA) IC 21 256 32-UFQFN Exposed Pad

General Description

The MachXO2 family of ultra low power, instant-on, non-volatile PLDs has six devices with densities ranging from 256 to

6864 Look-Up Tables (LUTs). In addition to LUT-based, low-cost programmable logic these devices feature Embedded

Block RAM (EBR), Distributed RAM, User Flash Memory (UFM), Phase Locked Loops (PLLs), preengineered source

synchronous I/O support, advanced configuration support including dual-boot capability and hardened versions of

commonly used functions such as SPI controller, I²C controller and timer/counter. These features allow these devices to

be used in low cost, high volume consumer and system applications.

The MachXO2 devices are designed on a 65 nm non-volatile low power process. The device architecture has several

features such as programmable low swing differential I/Os and the ability to turn off I/O banks, on-chip PLLs and

oscillators dynamically. These features help manage static and dynamic power consumption resulting in low static power

for all members of the family.

The MachXO2 devices are available in two versions – ultra low power (ZE) and high performance (HC and HE) devices.

The ultra low power devices are offered in three speed grades –1, –2 and –3, with –3 being the fastest. Similarly, the

high-performance devices are offered in three speed grades: –4, –5 and –6, with –6 being the fastest. HC devices have an

internal linear voltage regulator which supports external VCC supply voltages of 3.3 V or 2.5 V. ZE and HE devices only

accept 1.2 V as the external VCC supply voltage. With the exception of power supply voltage all three types of devices

(ZE, HC and HE) are functionally compatible and pin compatible with each other.

The MachXO2 PLDs are available in a broad range of advanced halogen-free packages ranging from the space saving

2.5 mm x 2.5 mm WLCSP to the 23 mm x 23 mm fpBGA. MachXO2 devices support density migration within the same

package. Table 1-1 shows the LUT densities, package and I/O options, along with other key parameters.

The pre-engineered source synchronous logic implemented in the MachXO2 device family supports a broad range of

interface standards, including LPDDR, DDR, DDR2 and 7:1 gearing for display I/Os.

The MachXO2 devices offer enhanced I/O features such as drive strength control, slew rate control, PCI compati bility,

bus-keeper latches, pull-up resistors, pull-down resistors, open drain outputs and hot socketing. Pull-up, pull-down and

bus-keeper features are controllable on a“per-pin”basis.

A user-programmable internal oscillator is included in MachXO2 devices. The clock output from this oscillator may be

divided by the timer/counter for use as clock input in functions such as LED control, key-board scanner and sim-ilar state

machines.

The MachXO2 devices also provide flexible, reliable and secure configuration from on-chip Flash memory. These devices

can also configure themselves from external SPI Flash or be configured by an external master through the JTAG test

access port or through the I2C port. Additionally, MachXO2 devices support dual-boot capability (using external Flash

memory) and remote field upgrade (TransFR) capability.

Lattice provides a variety of design tools that allow complex designs to be efficiently implemented using the MachXO2

family of devices. Popular logic synthesis tools provide synthesis library support for MachXO2. Lattice design tools use the

synthesis tool output along with the user-specified preferences and constraints to place and route the design in the

MachXO2 device. These tools extract the timing from the routing and back-annotate it intothe design for timing

verification.

Lattice provides many pre-engineered IP (Intellectual Property) LatticeCORE™ modules, including a number of reference

designs licensed free of charge, optimized for the MachXO2 PLD family. By using these configurable soft core IP cores as

standardized blocks, users are free to concentrate on the unique aspects of their design, increasing their productivity.

Features

• Flexible Logic Architecture

      Six devices with 256 to 6864 LUT4s and 18 to 334 I/Os

• Ultra Low Power Devices

      Advanced 65 nm low power process

      As low as 22 µW standby power

      Programmable low swing differential I/Os

      Stand-by mode and other power saving options

• Embedded and Distributed Memory

      Up to 240 kbits sysMEM™ Embedded BlockRAM

      Up to 54 kbits Distributed RAM

      Dedicated FIFO control logic

• On-Chip User Flash Memory

      Up to 256 kbits of User Flash Memory

      100,000 write cycles

      Accessible through WISHBONE, SPI, I2C and JTAG interfaces

      Can be used as soft processor PROM or as Flash memory

• Pre-Engineered Source Synchronous I/O

      DDR registers in I/O cells

      Dedicated gearing logic

      7:1 Gearing for Display I/Os

      Generic DDR, DDRX2, DDRX4

      Dedicated DDR/DDR2/LPDDR memory with DQS support

• High Performance, Flexible I/O Buffer

      Programmable sysIO™ buffer supports wide range of interfaces:

      – LVCMOS 3.3/2.5/1.8/1.5/1.2

      – LVTTL

      – PCI

      – LVDS, Bus-LVDS, MLVDS, RSDS, LVPECL

      – SSTL 25/18

      – HSTL 18

      – Schmitt trigger inputs, up to 0.5 V hysteresis

      I/Os support hot socketing

      On-chip differential termination

      Programmable pull-up or pull-down mode

• Flexible On-Chip Clocking

      Eight primary clocks

      Up to two edge clocks for high-speed I/O interfaces (top and bottom sides only)

      Up to two analog PLLs per device with fractional-n frequency synthesis

      – Wide input frequency range (7 MHz to 400 MHz)

• Non-volatile, Infinitely Reconfigurable

      Instant-on – powers up in microseconds

      Single-chip, secure solution

      Programmable through JTAG, SPI or I²C

      Supports background programming of non-vola-tile memory

      Optional dual boot with external SPI memory

• TransFR™ Reconfiguration

      In-field logic update while system operates

• Enhanced System Level Support

      On-chip hardened functions: SPI, I²C, timer/counter

      On-chip oscillator with 5.5% accuracy

      Unique TraceID for system tracking

      One Time Programmable (OTP) mode

      Single power supply with extended operating range

      IEEE Standard 1149.1 boundary scan

      IEEE 1532 compliant in-system programming

• Broad Range of Package Options

      TQFP, WLCSP, ucBGA, csBGA, caBGA, ftBGA, fpBGA, QFN package options

      Small footprint package options

      – As small as 2.5 mm x 2.5 mm

      Density migration supported

      Advanced halogen-free packaging

How to choose FPGA for your project?

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MachXO2 Field Programmable Gate Array (FPGA) IC 104 65536 1280 132-LFBGA, CSPBGA

General Description

The MachXO2 family of ultra low power, instant-on, non-volatile PLDs has six devices with densities ranging from 256 to

6864 Look-Up Tables (LUTs). In addition to LUT-based, low-cost programmable logic these devices feature Embedded

Block RAM (EBR), Distributed RAM, User Flash Memory (UFM), Phase Locked Loops (PLLs), preengineered source

synchronous I/O support, advanced configuration support including dual-boot capability and hardened versions of

commonly used functions such as SPI controller, I²C controller and timer/counter. These features allow these devices to

be used in low cost, high volume consumer and system applications.

The MachXO2 devices are designed on a 65 nm non-volatile low power process. The device architecture has several

features such as programmable low swing differential I/Os and the ability to turn off I/O banks, on-chip PLLs and

oscillators dynamically. These features help manage static and dynamic power consumption resulting in low static power

for all members of the family.

The MachXO2 devices are available in two versions – ultra low power (ZE) and high performance (HC and HE) devices.

The ultra low power devices are offered in three speed grades –1, –2 and –3, with –3 being the fastest. Similarly, the

high-performance devices are offered in three speed grades: –4, –5 and –6, with –6 being the fastest. HC devices have an

internal linear voltage regulator which supports external VCC supply voltages of 3.3 V or 2.5 V. ZE and HE devices only

accept 1.2 V as the external VCC supply voltage. With the exception of power supply voltage all three types of devices

(ZE, HC and HE) are functionally compatible and pin compatible with each other.

The MachXO2 PLDs are available in a broad range of advanced halogen-free packages ranging from the space saving

2.5 mm x 2.5 mm WLCSP to the 23 mm x 23 mm fpBGA. MachXO2 devices support density migration within the same

package. Table 1-1 shows the LUT densities, package and I/O options, along with other key parameters.

The pre-engineered source synchronous logic implemented in the MachXO2 device family supports a broad range of

interface standards, including LPDDR, DDR, DDR2 and 7:1 gearing for display I/Os.

The MachXO2 devices offer enhanced I/O features such as drive strength control, slew rate control, PCI compati bility,

bus-keeper latches, pull-up resistors, pull-down resistors, open drain outputs and hot socketing. Pull-up, pull-down and

bus-keeper features are controllable on a“per-pin”basis.

A user-programmable internal oscillator is included in MachXO2 devices. The clock output from this oscillator may be

divided by the timer/counter for use as clock input in functions such as LED control, key-board scanner and sim-ilar state

machines.

The MachXO2 devices also provide flexible, reliable and secure configuration from on-chip Flash memory. These devices

can also configure themselves from external SPI Flash or be configured by an external master through the JTAG test

access port or through the I2C port. Additionally, MachXO2 devices support dual-boot capability (using external Flash

memory) and remote field upgrade (TransFR) capability.

Lattice provides a variety of design tools that allow complex designs to be efficiently implemented using the MachXO2

family of devices. Popular logic synthesis tools provide synthesis library support for MachXO2. Lattice design tools use the

synthesis tool output along with the user-specified preferences and constraints to place and route the design in the

MachXO2 device. These tools extract the timing from the routing and back-annotate it intothe design for timing

verification.

Lattice provides many pre-engineered IP (Intellectual Property) LatticeCORE™ modules, including a number of reference

designs licensed free of charge, optimized for the MachXO2 PLD family. By using these configurable soft core IP cores as

standardized blocks, users are free to concentrate on the unique aspects of their design, increasing their productivity.

Features

• Flexible Logic Architecture

      Six devices with 256 to 6864 LUT4s and 18 to 334 I/Os

• Ultra Low Power Devices

      Advanced 65 nm low power process

      As low as 22 µW standby power

      Programmable low swing differential I/Os

      Stand-by mode and other power saving options

• Embedded and Distributed Memory

      Up to 240 kbits sysMEM™ Embedded BlockRAM

      Up to 54 kbits Distributed RAM

      Dedicated FIFO control logic

• On-Chip User Flash Memory

      Up to 256 kbits of User Flash Memory

      100,000 write cycles

      Accessible through WISHBONE, SPI, I2C and JTAG interfaces

      Can be used as soft processor PROM or as Flash memory

• Pre-Engineered Source Synchronous I/O

      DDR registers in I/O cells

      Dedicated gearing logic

      7:1 Gearing for Display I/Os

      Generic DDR, DDRX2, DDRX4

      Dedicated DDR/DDR2/LPDDR memory with DQS support

• High Performance, Flexible I/O Buffer

      Programmable sysIO™ buffer supports wide range of interfaces:

      – LVCMOS 3.3/2.5/1.8/1.5/1.2

      – LVTTL

      – PCI

      – LVDS, Bus-LVDS, MLVDS, RSDS, LVPECL

      – SSTL 25/18

      – HSTL 18

      – Schmitt trigger inputs, up to 0.5 V hysteresis

      I/Os support hot socketing

      On-chip differential termination

      Programmable pull-up or pull-down mode

• Flexible On-Chip Clocking

      Eight primary clocks

      Up to two edge clocks for high-speed I/O interfaces (top and bottom sides only)

      Up to two analog PLLs per device with fractional-n frequency synthesis

      – Wide input frequency range (7 MHz to 400 MHz)

• Non-volatile, Infinitely Reconfigurable

      Instant-on – powers up in microseconds

      Single-chip, secure solution

      Programmable through JTAG, SPI or I²C

      Supports background programming of non-vola-tile memory

      Optional dual boot with external SPI memory

• TransFR™ Reconfiguration

      In-field logic update while system operates

• Enhanced System Level Support

      On-chip hardened functions: SPI, I²C, timer/counter

      On-chip oscillator with 5.5% accuracy

      Unique TraceID for system tracking

      One Time Programmable (OTP) mode

      Single power supply with extended operating range

      IEEE Standard 1149.1 boundary scan

      IEEE 1532 compliant in-system programming

• Broad Range of Package Options

      TQFP, WLCSP, ucBGA, csBGA, caBGA, ftBGA, fpBGA, QFN package options

      Small footprint package options

      – As small as 2.5 mm x 2.5 mm

      Density migration supported

      Advanced halogen-free packaging

How to choose FPGA for your project?

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MachXO Field Programmable Gate Array (FPGA) IC 113 640 144-LQFP

General Description

The MachXO family architecture contains an array of logic blocks surrounded by Programmable I/O (PIO). Some devices

in this family have sysCLOCK PLLs and blocks of sysMEM™ Embedded Block RAM (EBRs). 

The logic blocks are arranged in a two-dimensional grid with rows and columns. The EBR blocks are arranged in a column

to the left of the logic array. The PIO cells are located at the periphery of the device, arranged into Banks. The PIOs utilize

a flexible I/O buffer referred to as a sysIO interface that supports operation with a variety of inter-face standards. The

blocks are connected with many vertical and horizontal routing channel resources. The place and route software tool

automatically allocates these routing resources.

There are two kinds of logic blocks, the Programmable Functional Unit (PFU) and the Programmable Functional unit

without RAM (PFF). The PFU contains the building blocks for logic, arithmetic, RAM, ROM, and register func-tions. The

PFF block contains building blocks for logic, arithmetic, ROM, and register functions. Both the PFU and PFF blocks are

optimized for flexibility, allowing complex designs to be implemented quickly and effectively. Logic blocks are arranged in

a two-dimensional array. Only one type of block is used per row.

In the MachXO family, the number of sysIO Banks varies by device. There are different types of I/O Buffers on dif-ferent

Banks. See the details in later sections of this document. The sysMEM EBRs are large, dedicated fast memory blocks; these

blocks are found only in the larger devices. These blocks can be configured as RAM, ROM or FIFO. FIFO support includes

dedicated FIFO pointer and flag“hard”control logic to minimize LUT use.

The MachXO registers in PFU and sysI/O can be configured to be SET or RESET. After power up and device is configured,

the device enters into user mode with these registers SET/RESET according to the configuration set-ting, allowing device

entering to a known state for predictable system function.

The MachXO architecture provides up to two sysCLOCK™ Phase Locked Loop (PLL) blocks on larger devices.These blocks

are located at either end of the memory blocks. The PLLs have multiply, divide, and phase shifting capabilities that are

used to manage the frequency and phase relationships of the clocks.

Every device in the family has a JTAG Port that supports programming and configuration of the device as well as access to

the user logic. The MachXO devices are available for operation from 3.3V, 2.5V, 1.8V, and 1.2V power supplies, providing

easy integration into the overall system.

Features

• Non-volatile, Infinitely Reconfigurable

      Instant-on – powers up in microseconds

      Single chip, no external configuration memory required

      Excellent design security, no bit stream to intercept

      Reconfigure SRAM based logic in milliseconds

      SRAM and non-volatile memory programmable through JTAG port

      Supports background programming of non-volatile memory

• Sleep Mode

      Allows up to 100x static current reduction

• TransFR™ Reconfiguration (TFR)

      In-field logic update while system operates

• High I/O to Logic Density

      256 to 2280 LUT4s

      73 to 271 I/Os with extensive package options

      Density migration supported

      Lead free/RoHS compliant packaging

• Embedded and Distributed Memory

      Up to 27.6 Kbits sysMEM™ Embedded Block RAM

      Up to 7.7 Kbits distributed RAM

      Dedicated FIFO control logic

• Flexible I/O Buffer

      Programmable sysIO™ buffer supports wide range of interfaces:

      ——LVCMOS 3.3/2.5/1.8/1.5/1.2

      ——LVTTL

      ——PCI

      ——LVDS, Bus-LVDS, LVPECL, RSDS

• sysCLOCK™ PLLs

      Up to two analog PLLs per device

      Clock multiply, divide, and phase shifting

• System Level Support

      IEEE Standard 1149.1 Boundary Scan

      Onboard oscillator

      Devices operate with 3.3V, 2.5V, 1.8V or 1.2V power supply

      IEEE 1532 compliant in-system programming

How to choose FPGA for your project?

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MachXO3 Field Programmable Gate Array (FPGA) IC 206 245760 6864 256-LFBGA

General Description

MachXO3™ device family is an Ultra-Low Density family that supports the most advanced programmable bridging and

I/O expansion. It has the breakthrough I/O density and the lowest cost per I/O. The device I/O features have the

integrated support for latest industry standard I/O.

The MachXO3L/LF family of low power, instant-on, non-volatile PLDs has five devices with densities ranging from 640 to

9400 Look-Up Tables (LUTs). In addition to LUT-based, low-cost programmable logic these devices feature Embedded

Block RAM (EBR), Distributed RAM, Phase Locked Loops (PLLs), pre-engineered source synchronous I/O support, advanced

configuration support including dual-boot capability and hardened versions of commonly used functions such as SPI

controller, I2C controller and timer/counter. MachXO3LF devices also support User Flash Memory (UFM). These features

allow these devices to be used in low cost, high volume applications such as consumer electronics, compute and storage,

wireless communications, industrial control, and automotive systems.

The MachXO3L/LF devices are designed on a 65 nm non-volatile low power process. The device architecture has several

features such as programmable low swing differential I/O and the ability to turn off I/O banks, on-chip PLLs and

oscillators dynamically. These features help manage static and dynamic power consumption resulting in low static power

for all members of the family.

The MachXO3L/LF devices are available in two versions C and E with two speed grades: -5 and -6, with -6 being the

fastest. C devices have an internal linear voltage regulator which supports external VCC supply voltages of 3.3 V or 2.5 V.

E devices only accept 1.2 V as the external VCC supply voltage. With the exception of power supply voltage both C and E

are functionally compatible with each other.

The MachXO3L/LF PLDs are available in a broad range of advanced halogen-free packages ranging from the space saving

2.5 x 2.5 mm WLCSP to the 19 x 19 mm caBGA. MachXO3L/LF devices support density migration within the same package.

Table 1.1 shows the LUT densities, package and I/O options, along with other key parameters.

The MachXO3L/LF devices offer enhanced I/O features  such as drive strength control, slew rate control, PCI compatibility,

bus-keeper latches, pull-up resistors, pull-down resistors, open drain outputs and hot socketing. Pull-up, pull-down and

bus-keeper features are controllable on a “per-pin” basis. A user-programmable internal oscillator is included in

MachXO3L/LF devices. The clock output from this oscillator may be divided by the timer/counter for use as clock input in

functions such as LED control, keyboard scanner and similar state machines.

The MachXO3L/LF devices also provide flexible, reliable and secure configuration from on-chip NVCM/Flash. These

devices can also configure themselves from external SPI Flash or be configured by an external master through the JTAG

test access port or through the I²C port. Additionally, MachXO3L/LF devices support dual-boot capability (using external

Flash memory) and remote field upgrade (TransFR) capability.

Lattice provides a variety of design tools that allow complex designs to be efficiently implemented using the

MachXO3L/LF family of devices. Popular logic synthesis tools provide synthesis library support for MachXO3L/LF. Lattice

design tools use the synthesis tool output along with the user-specified preferences and constraints to place and route

the design in the MachXO3L/LF device. These tools extract the timing from the routing and back-annotate it into the

design for timing verification.

Lattice provides many pre-engineered IP (Intellectual Property) LatticeCORE™ modules, including a number of reference

designs licensed free of charge, optimized for the MachXO3L/LF PLD family. By using these configurable soft core IP

cores as standardized blocks, users are free to concentrate on the unique aspects of their design, increasing their

productivity.

Features

• Solutions

      Smallest footprint, lowest power, high data throughput bridging solutions for mobile applications

      Optimized footprint, logic density, I/O count, I/O performance devices for I/O management and logic applications

      High I/O logic, lowest cost I/O, high I/O devices for I/O expansion applications

• Flexible Architecture

      Logic Density ranging from 64 to 9.4 k LUT4

      High I/O to LUT ratio with up to 384 I/O pins

• Advanced Packaging

      0.4 mm pitch: 1 k to 4 k densities in very small footprint WLCSP (2.5 mm × 2.5 mm to 3.8 mm × 3.8 mm) with 28 to

      63 I/O

      0.5 mm pitch: 640 to 9.4 k LUT densities in 6 mm x 6 mm to 10 mm x 10 mm BGA packages with up to281 I/O

      0.8 mm pitch: 1 k to 9.4 k densities with up to 384 I/O in BGA packages

• Pre-Engineered Source Synchronous I/O

      DDR registers in I/O cells

      Dedicated gearing logic

      7:1 Gearing for Display I/O

      Generic DDR, DDRx2, DDRx4

• High Performance, Flexible I/O Buffer

      Programmable sysI/O™ buffer supports wide range of interfaces:

            LVCMOS 3.3/2.5/1.8/1.5/1.2

            LVTTL

            LVDS, Bus-LVDS, MLVDS, LVPECL

            MIPI D-PHY Emulated

            Schmitt trigger inputs, up to 0.5 V hysteresis

      Ideal for I/O bridging applications

      I/O support hot socketing

      On-chip differential termination

      Programmable pull-up or pull-down mode

• Flexible On-Chip Clocking

      Eight primary clocks

      Up to two edge clocks for high-speed I/O interfaces (top and bottom sides only)

      Up to two analog PLLs per device with fractional-n frequency synthesis

            Wide input frequency range (7 MHz to 400 MHz).

• Non-volatile, Multi-time Programmable

      Instant-on

            Powers up in microseconds

      Optional dual boot with external SPI memory

      Single-chip, secure solution

      Programmable through JTAG, SPI or I2C

      MachXO3L includes multi-time programmable NVCM

      MachXO3LF reconfigurable Flash includes 100,000 write/erase cycle for commercial/industrial devices and 10,000 for

      automotive devices

      Supports background programming of non volatile memory

• TransFR Reconfiguration

      In-field logic update while I/O holds the system state

• Enhanced System Level Support

      On-chip hardened functions: SPI, I2C, timer/counter

      On-chip oscillator with 5.5% accuracy for commercial/industrial devices

      Unique TraceID for system tracking

      Single power supply with extended operatingrange

      IEEE Standard 1149.1 boundary scan

      IEEE 1532 compliant in-system programming

• Applications

      Consumer Electronics

      Compute and Storage

      Wireless Communications

      Industrial Control Systems

      Automotive System

• Low Cost Migration Path

      Migration from the Flash based MachXO3LF to the NVCM based MachXO3L

      Pin compatible and equivalent timing

How to choose FPGA for your project?

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CrossLink-NX™ Field Programmable Gate Array (FPGA) IC 72 1548288 39000 121-VFBGA, CSPBGA

General Description

CrossLink™-NX family of low-power FPGAs can be used in a wide range of applications, and are optimized for bridging and

processing needs in Embedded Vision applications – supporting a variety of high bandwidth sensor and display interfaces,

video processing and machine learning inferencing. It is built on Lattice Nexus FPGA platform, using low-power 28 nm

FD-SOI technology. It combines the extreme flexibility of an FPGA with the low power and high reliability (due to extremely

low SER) of FD-SOI technology, and offers small footprint package options.

CrossLink-NX supports a variety of interfaces including MIPI D-PHY (CSI-2, DSI), LVDS, SLVS, subLVDS, PCI Express (Gen1,

Gen2), SGMII (Gigabit Ethernet), and more.

Processing features of CrossLink-NX include up to 39K Logic Cells, 56 18x18 multipliers, 2.9 Mb of embedded memory

(consisting of EBR and LRAM blocks), distributed memory, DRAM interfaces (supporting DDR3, DDR3L, LPDDR2, and

LPDDR3 up to 1066 Mbps x16 data width).

CrossLink-NX FPGAs support fast configuration of its reconfigurable SRAM-based logic fabric, and ultra-fast configuration

(in under 3 ms) of its programmable sysI/O™. Security features to secure user designs include bitstream encryption and

password protection. In addition to the high reliability inherent to FD-SOI technology (due to its extremely low SER), active

reliability features such as built-in frame-based SED/SEC (for SRAM-based logic fabric), and ECC (for EBR and LRAM) are

also supported. Built-in ADC is available in each device for system monitoring functions.

Lattice Radiant™ design software allows large complex user designs to be efficiently implemented on CrossLink-NX FPGA

family. Synthesis library support for CrossLink-NX devices is available for popular logic synthesis tools. Radiant tools use the

synthesis tool output along with constraints from its floor planning tools, to place and route the user design in

CrossLink-NX device. The tools extract timing from the routing, and back-annotate it into the design for timing verification.

Lattice provides many pre-engineered IP (Intellectual Property) modules for CrossLink-NX family. By using these

configurable soft IP cores as standardized blocks, you are free to concentrate on the unique aspects of your design,

increasing your productivity.

Features

• Programmable Architecture

      17K to 39K logic cells

      24 to 56 18 x 18 multipliers (in sysDSP™ blocks)

      2.5 to 2.9 Mb of embedded memory blocks (EBR, LRAM)

      36 to 192 programmable sysI/O (High Performance and Wide Range I/O)

• MIPI D-PHY

      Up to two hardened 4-lane MIPI D-PHY interfaces

            Up to eight lanes total

            Transmit or receive

            Supports CSI-2, DSI

            20 Gbps aggregate bandwidth

            2.5 Gbps per lane, 10 Gbps per D-PHY interface

      Additional Soft D-PHY interfaces supported by High Performance (HP) sysI/O

            Transmit or receive

            Supports CSI-2, DSI

            Up to 1.5 Gbps per lane

• Programmable sysI/O supports wide variety of interfaces

      High Performance (HP) on bottom I/O dual rank

            Supports up to 1.8 V VCCIO

            Mixed voltage support (1.0 V, 1.2 V, 1.5 V, 1.8 V)

            High-speed differential up to 1.5 Gbps

            Supports soft D-PHY (Tx/Rx), LVDS 7:1 (Tx/Rx), SLVS (Tx/Rx), subLVDS (Rx)

            Supports SGMII (Gb Ethernet) – 2 channels (Tx/Rx) at 1.25 Gbps

            Dedicated DDR3/DDR3L and LPDDR2/LPDDR3 memory support with DQS logic, up to 1066 Mbps data-rate and

            x16 data-width

      Wide Range (WR) on Left, Right and Top I/O Banks

            Supports up to 3.3 V VCCIO

            Mixed voltage support (1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V)

            Programmable slew rate (slow, med, fast)

            Controlled impedance mode

            Emulated LVDS support

            Hot-socketing

• Power Modes – Low Power versus High Performance

      User selectable

      Low-Power mode for power and/or thermal challenges

      High-Performance mode for faster processing

• Small footprint package options

      4 x 4 mm2to 10 x 10 mm2 package options

• 2x SGMII CDR at up to 1.25 Gbps – to support 2 channels SGMII using HP I/O

      CDR for RX

      8b/10b decoding

      Independent Loss of Lock (LOL) detector for each CDR block

• sysCLOCK™ analog PLLs

      Three in 39K LC and two in 17K LC device

      Six outputs per PLL

      Fractional N

      Programmable and dynamic phase control

• sysDSP Enhanced DSP blocks

      Hardened pre-adder

      Dynamic Shift for AI/ML support

      Four 18 x 18, eight 9 x 9, two 18 x 36, or 36 x 36

      Advanced 18 x 36, two 18 x 18, or four 8 x 8 MAC

• Flexible memory resources

      Up to 1.5 Mb sysMEM™ Embedded Block RAM EBR)

      Programmable width

      ECC

      FIFO

      80k to 240k bits distributed RAM

      Large RAM Blocks

            0.5 Mbits per block

            Up to five blocks (2.5 Mb total) per device

• SERDES – PCIe Gen2 x1 channel (Tx/Rx) hard IP in 39K LC device

      Hard IP supports

            Gen1, Gen2, Multi-Function, End Point, Root Complex

            APB control bus

            AHB-Lite for data bus

• Internal bus interface support

      APB control bus

      AHB-Lite for data bus

      AXI4-streaming 

• Configuration – Fast, Secure

      SPI – x1, x2, x4 up to 150 MHz

            Master and Slave SPI support

      JTAG

      I²C and I3C

      Ultrafast I/O configuration for instant-on support

      Less than 15 ms full device configuration for LIFCL-40

      Bitstream Security

            Encryption

• Cryptographic engine

      Bitstream encryption – using AES-256

      Bitstream authentication – using ECDSA

      Hashing algorithms – SHA, HMAC

      True Random Number Generator

      AES 128/256 Encryption

• Single Event Upset (SEU) Mitigation Support

      Extremely low Soft Error Rate (SER) due to FD SOI technology

      Soft Error Detect – Embedded hard macro

      Soft Error Correction – Without stopping user operation

      Soft Error Injection – Emulate SEU event to debug system error handling

• ADC – 1 MSPS, 12-bit SAR

      2 ADCs per device

      3 Continuous-time Comparators

      Simultaneous sampling

• System Level Support

      IEEE 1149.1 and IEEE 1532 compliant

      Reveal Logic Analyzer

      On-chip oscillator for initialization and general use

      1.0 V core power supply

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ECP5-5G Field Programmable Gate Array (FPGA) IC 205 3833856 84000 381-FBGA

General Description

The ECP5™/ECP5-5G™ family of FPGA devices is optimized to deliver high performance features such as an enhanced DSP

architecture, high speed SERDES (Serializer/Deserializer), and high speed source synchronous interfaces, in an economical

FPGA fabric. This combination is achieved through advances in device architecture and the use of 40 nm technology

making the devices suitable for high-volume, high-speed, and low-cost applications.

The ECP5/ECP5-5G device family covers look-up-table (LUT) capacity to 84K logic elements and supports up to 365 user

I/O. The ECP5/ECP5-5G device family also offers up to 156 18 x 18 multipliers and a wide range of parallel I/O standards.

The ECP5/ECP5-5G FPGA fabric is optimized high performance with low power and low cost in mind. The ECP5/ ECP5-5G

devices utilize reconfigurable SRAM logic technology and provide popular building blocks such as LUT-based logic,

distributed and embedded memory, Phase-Locked Loops (PLLs), Delay-Locked Loops (DLLs), pre-engineered source

synchronous I/O support, enhanced sysDSP slices and advanced configuration support, including encryption and dual-boot

capabilities.

The pre-engineered source synchronous logic implemented in the ECP5/ECP5-5G device family supports a broad range of

interface standards including DDR2/3, LPDDR2/3, XGMII, and 7:1 LVDS.

The ECP5/ECP5-5G device family also features high speed SERDES with dedicated Physical Coding Sublayer (PCS) functions.

High jitter tolerance and low transmit jitter allow the SERDES plus PCS blocks to be configured to support an array of

popular data protocols including PCI Express, Ethernet (XAUI, GbE, and SGMII) and CPRI. Transmit De-emphasis with

pre- and post-cursors, and Receive Equalization settings make the SERDES suitable for transmission and reception over

various forms of media.

The ECP5/ECP5-5G devices also provide flexible, reliable and secure configuration options, such as dual-boot capability,

bit-stream encryption, and TransFR field upgrade features.

ECP5-5G family devices have made some enhancement in the SERDES compared to ECP5UM devices. These enhancements

increase the performance of the SERDES to up to 5 Gb/s data rate.

The ECP5-5G family devices are pin-to-pin compatible with the ECP5UM devices. These allows a migration path for you to

port designs from ECP5UM to ECP5-5G devices to get higher performance.

The Lattice Diamond™ design software allows large complex designs to be efficiently implemented using the ECP5/ECP5-5G

FPGA family. Synthesis library support for ECP5/ECP5-5G devices is available for popular logic synthesis tools. The

Diamond tools use the synthesis tool output along with the constraints from its floor planning tools to place and route the

design in the ECP5/ECP5-5G device. The tools extract the timing from the routing and back-annotate it into the design for

timing verification.

Lattice provides many pre-engineered IP (Intellectual Property) modules for the ECP5/ECP5-5G family. Byusing these

configurable soft core IPs as standardized blocks, designers are free to concentrate on the unique aspects of their design,

increasing their productivity.

Features

• Higher Logic Density for Increased System Integration

      12K to 84K LUTs

      197 to 365 user programmable I/O

• Embedded SERDES

      270 Mb/s, up to 3.2 Gb/s, SERDES interface (ECP5)

      270 Mb/s, up to 5.0 Gb/s, SERDES interface (ECP5-5G)

      Supports eDP in RDR (1.62 Gb/s) and HDR

      (2.7 Gb/s)

      Up to four channels per device: PCI Express, Ethernet (1GbE, SGMII, XAUI), and CPRI

• sysDSP™

      Fully cascadable slice architecture

      12 to 160 slices for high performance multiply and accumulate

      Powerful 54-bit ALU operations

      Time Division Multiplexing MAC Sharing

      Rounding and truncation

      Each slice supports

            Half 36 x 36, two 18 x 18 or four 9 x 9 multipliers

            Advanced 18 x 36 MAC and 18 x 18 Multiply-Multiply-Accumulate (MMAC) operations

• Flexible Memory Resources

      Up to 3.744 Mb sysMEM™ Embedded Block

      RAM (EBR)

      194K to 669K bits distributed RAM

• sysCLOCK Analog PLLs and DLLs

      Four DLLs and four PLLs in LFE5-45 and LFE5-85; two DLLs and two PLLs in LFE5-25 and LFE5-12

• Pre-Engineered Source Synchronous I/O

      DDR registers in I/O cells

      Dedicated read/write levelling functionality

      Dedicated gearing logic

      Source synchronous standards support

      ADC/DAC, 7:1 LVDS, XGMII

      High Speed ADC/DAC devices

      Dedicated DDR2/DDR3 and LPDDR2/LPDDR3 memory support with DQS logic, up to 800 Mb/s data-rate

• Programmable sysI/O™ Buffer Supports Wide Range of Interfaces

      On-chip termination

      LVTTL and LVCMOS 33/25/18/15/12

      SSTL 18/15 I, II

      HSUL12

      LVDS, Bus-LVDS, LVPECL, RSDS, MLVDS

      subLVDS and SLVS, SoftIP MIPI D-PHY receiver/transmitter interfaces

• Flexible Device Configuration

      Shared bank for configuration I/O

      SPI boot flash interface

      Dual-boot images supported

      Slave SPI

      TransFR™ I/O for simple field updates

• Single Event Upset (SEU) Mitigation Support

      Soft Error Detect – Embedded hard macro

      Soft Error Correction – Without stopping user operation

      Soft Error Injection – Emulate SEU event to debug system error handling

• System Level Support

      IEEE 1149.1 and IEEE 1532 compliant

      Reveal Logic Analyzer

      On-chip oscillator for initialization and general use

      V core power supply for ECP5, 1.2 V core power supply for ECP5UM5G

How to choose FPGA for your project?

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