Lattice Semiconductor Corporation

iCE40™ LP Field Programmable Gate Array (FPGA) IC 63 131072 7680 81-VFBGA

General Description

The iCE40 family architecture contains an array of Programmable Logic Blocks (PLB), sysCLOCK™ PLLs, Nonvolatile

Programmable Configuration Memory (NVCM) and blocks of sysMEM™ Embedded Block RAM (EBR) surrounded by

Programmable I/O (PIO). 

The logic blocks, Programmable Logic Blocks (PLB) and sysMEM EBR blocks, are arranged in a two-dimensional grid with

rows and columns. Each column has either logic blocks or EBR blocks. The PIO cells are located at the periphery of the

device, arranged in banks. The PLB contains the building blocks for logic, arithmetic, and register functions. The PIOs

utilize a flexible I/O buffer referred to as a sysIO buffer that supports operation with a variety of interface standards. The

blocks are connected with many vertical and horizontal routing channel resources. Theplace and route software tool

automatically allocates these routing resources.

In the iCE40 family, there are up to four independent sysIO banks. Note on some packages VCCIO banks are tied together.

There are different types of I/O buffers on the different banks. Refer to the details in later sections of this document.

The sysMEM EBRs are large 4 kbit, dedicated fast memory blocks. These blocks can be configured as RAM, ROM or FIFO.

The iCE40 architecture also provides up to two sysCLOCK Phase Locked Loop (PLL) blocks. The PLLs have multiply, divide,

and phase shifting capabilities that are used to manage the frequency and phase relationships of the clocks.

Every device in the family has a SPI port that supports programming and configuration of the device. The iCE40 includes

on-chip, Nonvolatile Configuration Memory (NVCM).

Features

• Flexible Logic Architecture

      Five devices with 384 to 7,680 LUT4s and 10 to 206 I/Os

• Ultra Low Power Devices

      Advanced 40 nm low power process

      As low as 21 µA standby power

      Programmable low swing differential I/Os

• Embedded and Distributed Memory

      Up to 128 kbits sysMEM™ Embedded Block RAM

• Pre-Engineered Source Synchronous I/O

      DDR registers in I/O cells

• High Current LED Drivers

      Three High Current Drivers used for three different LEDs or one RGB LED

• High Performance, Flexible I/O Buffer

      Programmable sysIO™ buffer supports wide range of interfaces:

      — LVCMOS 3.3/2.5/1.8

      — LVDS25E, subLVDS

      — Schmitt trigger inputs, to 200 mV typical hysteresis

      Programmable pull-up mode

• Flexible On-Chip Clocking

      Eight low-skew global clock resources

      Up to two analog PLLs per device

• Flexible Device Configuration

      SRAM is configured through:

      — Standard SPI Interface

      — Internal Nonvolatile Configuration Memory (NVCM)

• Broad Range of Package Options

      WLCSP, QFN, VQFP, TQFP, ucBGA, caBGA,and csBGA package options

      Small footprint package options

      — As small as 1.40 mm x 1.48 mm

      Advanced halogen-free packaging

MachXO Field Programmable Gate Array (FPGA) IC 78 256 100-LQFP

General Description

The MachXO family architecture contains an array of logic blocks surrounded by Programmable I/O (PIO). Some devices

in this family have sysCLOCK PLLs and blocks of sysMEM™ Embedded Block RAM (EBRs). 

The logic blocks are arranged in a two-dimensional grid with rows and columns. The EBR blocks are arranged in a column

to the left of the logic array. The PIO cells are located at the periphery of the device, arranged into Banks. The PIOs utilize

a flexible I/O buffer referred to as a sysIO interface that supports operation with a variety of inter-face standards. The

blocks are connected with many vertical and horizontal routing channel resources. The place and route software tool

automatically allocates these routing resources.

There are two kinds of logic blocks, the Programmable Functional Unit (PFU) and the Programmable Functional unit

without RAM (PFF). The PFU contains the building blocks for logic, arithmetic, RAM, ROM, and register func-tions. The

PFF block contains building blocks for logic, arithmetic, ROM, and register functions. Both the PFU and PFF blocks are

optimized for flexibility, allowing complex designs to be implemented quickly and effectively. Logic blocks are arranged in

a two-dimensional array. Only one type of block is used per row.

In the MachXO family, the number of sysIO Banks varies by device. There are different types of I/O Buffers on dif-ferent

Banks. See the details in later sections of this document. The sysMEM EBRs are large, dedicated fast memory blocks; these

blocks are found only in the larger devices. These blocks can be configured as RAM, ROM or FIFO. FIFO support includes

dedicated FIFO pointer and flag“hard”control logic to minimize LUT use.

The MachXO registers in PFU and sysI/O can be configured to be SET or RESET. After power up and device is configured,

the device enters into user mode with these registers SET/RESET according to the configuration set-ting, allowing device

entering to a known state for predictable system function.

The MachXO architecture provides up to two sysCLOCK™ Phase Locked Loop (PLL) blocks on larger devices.These blocks

are located at either end of the memory blocks. The PLLs have multiply, divide, and phase shifting capabilities that are

used to manage the frequency and phase relationships of the clocks.

Every device in the family has a JTAG Port that supports programming and configuration of the device as well as access to

the user logic. The MachXO devices are available for operation from 3.3V, 2.5V, 1.8V, and 1.2V power supplies, providing

easy integration into the overall system.

Features

• Non-volatile, Infinitely Reconfigurable

      Instant-on – powers up in microseconds

      Single chip, no external configuration memory required

      Excellent design security, no bit stream to intercept

      Reconfigure SRAM based logic in milliseconds

      SRAM and non-volatile memory programmable through JTAG port

      Supports background programming of non-volatile memory

• Sleep Mode

      Allows up to 100x static current reduction

• TransFR™ Reconfiguration (TFR)

      In-field logic update while system operates

• High I/O to Logic Density

      256 to 2280 LUT4s

      73 to 271 I/Os with extensive package options

      Density migration supported

      Lead free/RoHS compliant packaging

• Embedded and Distributed Memory

      Up to 27.6 Kbits sysMEM™ Embedded Block RAM

      Up to 7.7 Kbits distributed RAM

      Dedicated FIFO control logic

• Flexible I/O Buffer

      Programmable sysIO™ buffer supports wide range of interfaces:

      ——LVCMOS 3.3/2.5/1.8/1.5/1.2

      ——LVTTL

      ——PCI

      ——LVDS, Bus-LVDS, LVPECL, RSDS

• sysCLOCK™ PLLs

      Up to two analog PLLs per device

      Clock multiply, divide, and phase shifting

• System Level Support

      IEEE Standard 1149.1 Boundary Scan

      Onboard oscillator

      Devices operate with 3.3V, 2.5V, 1.8V or 1.2V power supply

      IEEE 1532 compliant in-system programming

How to choose FPGA for your project?

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MachXO2 Field Programmable Gate Array (FPGA) IC 79 75776 2112 100-LQFP

General Description

The MachXO2 family of ultra low power, instant-on, non-volatile PLDs has six devices with densities ranging from 256 to

6864 Look-Up Tables (LUTs). In addition to LUT-based, low-cost programmable logic these devices feature Embedded

Block RAM (EBR), Distributed RAM, User Flash Memory (UFM), Phase Locked Loops (PLLs), preengineered source

synchronous I/O support, advanced configuration support including dual-boot capability and hardened versions of

commonly used functions such as SPI controller, I²C controller and timer/counter. These features allow these devices to

be used in low cost, high volume consumer and system applications.

The MachXO2 devices are designed on a 65 nm non-volatile low power process. The device architecture has several

features such as programmable low swing differential I/Os and the ability to turn off I/O banks, on-chip PLLs and

oscillators dynamically. These features help manage static and dynamic power consumption resulting in low static power

for all members of the family.

The MachXO2 devices are available in two versions – ultra low power (ZE) and high performance (HC and HE) devices.

The ultra low power devices are offered in three speed grades –1, –2 and –3, with –3 being the fastest. Similarly, the

high-performance devices are offered in three speed grades: –4, –5 and –6, with –6 being the fastest. HC devices have an

internal linear voltage regulator which supports external VCC supply voltages of 3.3 V or 2.5 V. ZE and HE devices only

accept 1.2 V as the external VCC supply voltage. With the exception of power supply voltage all three types of devices

(ZE, HC and HE) are functionally compatible and pin compatible with each other.

The MachXO2 PLDs are available in a broad range of advanced halogen-free packages ranging from the space saving

2.5 mm x 2.5 mm WLCSP to the 23 mm x 23 mm fpBGA. MachXO2 devices support density migration within the same

package. Table 1-1 shows the LUT densities, package and I/O options, along with other key parameters.

The pre-engineered source synchronous logic implemented in the MachXO2 device family supports a broad range of

interface standards, including LPDDR, DDR, DDR2 and 7:1 gearing for display I/Os.

The MachXO2 devices offer enhanced I/O features such as drive strength control, slew rate control, PCI compati bility,

bus-keeper latches, pull-up resistors, pull-down resistors, open drain outputs and hot socketing. Pull-up, pull-down and

bus-keeper features are controllable on a“per-pin”basis.

A user-programmable internal oscillator is included in MachXO2 devices. The clock output from this oscillator may be

divided by the timer/counter for use as clock input in functions such as LED control, key-board scanner and sim-ilar state

machines.

The MachXO2 devices also provide flexible, reliable and secure configuration from on-chip Flash memory. These devices

can also configure themselves from external SPI Flash or be configured by an external master through the JTAG test

access port or through the I2C port. Additionally, MachXO2 devices support dual-boot capability (using external Flash

memory) and remote field upgrade (TransFR) capability.

Lattice provides a variety of design tools that allow complex designs to be efficiently implemented using the MachXO2

family of devices. Popular logic synthesis tools provide synthesis library support for MachXO2. Lattice design tools use the

synthesis tool output along with the user-specified preferences and constraints to place and route the design in the

MachXO2 device. These tools extract the timing from the routing and back-annotate it intothe design for timing

verification.

Lattice provides many pre-engineered IP (Intellectual Property) LatticeCORE™ modules, including a number of reference

designs licensed free of charge, optimized for the MachXO2 PLD family. By using these configurable soft core IP cores as

standardized blocks, users are free to concentrate on the unique aspects of their design, increasing their productivity.

Features

• Flexible Logic Architecture

      Six devices with 256 to 6864 LUT4s and 18 to 334 I/Os

• Ultra Low Power Devices

      Advanced 65 nm low power process

      As low as 22 µW standby power

      Programmable low swing differential I/Os

      Stand-by mode and other power saving options

• Embedded and Distributed Memory

      Up to 240 kbits sysMEM™ Embedded BlockRAM

      Up to 54 kbits Distributed RAM

      Dedicated FIFO control logic

• On-Chip User Flash Memory

      Up to 256 kbits of User Flash Memory

      100,000 write cycles

      Accessible through WISHBONE, SPI, I2C and JTAG interfaces

      Can be used as soft processor PROM or as Flash memory

• Pre-Engineered Source Synchronous I/O

      DDR registers in I/O cells

      Dedicated gearing logic

      7:1 Gearing for Display I/Os

      Generic DDR, DDRX2, DDRX4

      Dedicated DDR/DDR2/LPDDR memory with DQS support

• High Performance, Flexible I/O Buffer

      Programmable sysIO™ buffer supports wide range of interfaces:

      – LVCMOS 3.3/2.5/1.8/1.5/1.2

      – LVTTL

      – PCI

      – LVDS, Bus-LVDS, MLVDS, RSDS, LVPECL

      – SSTL 25/18

      – HSTL 18

      – Schmitt trigger inputs, up to 0.5 V hysteresis

      I/Os support hot socketing

      On-chip differential termination

      Programmable pull-up or pull-down mode

• Flexible On-Chip Clocking

      Eight primary clocks

      Up to two edge clocks for high-speed I/O interfaces (top and bottom sides only)

      Up to two analog PLLs per device with fractional-n frequency synthesis

      – Wide input frequency range (7 MHz to 400 MHz)

• Non-volatile, Infinitely Reconfigurable

      Instant-on – powers up in microseconds

      Single-chip, secure solution

      Programmable through JTAG, SPI or I²C

      Supports background programming of non-vola-tile memory

      Optional dual boot with external SPI memory

• TransFR™ Reconfiguration

      In-field logic update while system operates

• Enhanced System Level Support

      On-chip hardened functions: SPI, I²C, timer/counter

      On-chip oscillator with 5.5% accuracy

      Unique TraceID for system tracking

      One Time Programmable (OTP) mode

      Single power supply with extended operating range

      IEEE Standard 1149.1 boundary scan

      IEEE 1532 compliant in-system programming

• Broad Range of Package Options

      TQFP, WLCSP, ucBGA, csBGA, caBGA, ftBGA, fpBGA, QFN package options

      Small footprint package options

      – As small as 2.5 mm x 2.5 mm

      Density migration supported

      Advanced halogen-free packaging

How to choose FPGA for your project?

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MachXO2 Field Programmable Gate Array (FPGA) IC 68 94208 4320 84-VFQFN Dual Rows, Exposed Pad

General Description

The MachXO2 family of ultra low power, instant-on, non-volatile PLDs has six devices with densities ranging from 256 to

6864 Look-Up Tables (LUTs). In addition to LUT-based, low-cost programmable logic these devices feature Embedded

Block RAM (EBR), Distributed RAM, User Flash Memory (UFM), Phase Locked Loops (PLLs), preengineered source

synchronous I/O support, advanced configuration support including dual-boot capability and hardened versions of

commonly used functions such as SPI controller, I²C controller and timer/counter. These features allow these devices to

be used in low cost, high volume consumer and system applications.

The MachXO2 devices are designed on a 65 nm non-volatile low power process. The device architecture has several

features such as programmable low swing differential I/Os and the ability to turn off I/O banks, on-chip PLLs and

oscillators dynamically. These features help manage static and dynamic power consumption resulting in low static power

for all members of the family.

The MachXO2 devices are available in two versions – ultra low power (ZE) and high performance (HC and HE) devices.

The ultra low power devices are offered in three speed grades –1, –2 and –3, with –3 being the fastest. Similarly, the

high-performance devices are offered in three speed grades: –4, –5 and –6, with –6 being the fastest. HC devices have an

internal linear voltage regulator which supports external VCC supply voltages of 3.3 V or 2.5 V. ZE and HE devices only

accept 1.2 V as the external VCC supply voltage. With the exception of power supply voltage all three types of devices

(ZE, HC and HE) are functionally compatible and pin compatible with each other.

The MachXO2 PLDs are available in a broad range of advanced halogen-free packages ranging from the space saving

2.5 mm x 2.5 mm WLCSP to the 23 mm x 23 mm fpBGA. MachXO2 devices support density migration within the same

package. Table 1-1 shows the LUT densities, package and I/O options, along with other key parameters.

The pre-engineered source synchronous logic implemented in the MachXO2 device family supports a broad range of

interface standards, including LPDDR, DDR, DDR2 and 7:1 gearing for display I/Os.

The MachXO2 devices offer enhanced I/O features such as drive strength control, slew rate control, PCI compati bility,

bus-keeper latches, pull-up resistors, pull-down resistors, open drain outputs and hot socketing. Pull-up, pull-down and

bus-keeper features are controllable on a“per-pin”basis.

A user-programmable internal oscillator is included in MachXO2 devices. The clock output from this oscillator may be

divided by the timer/counter for use as clock input in functions such as LED control, key-board scanner and sim-ilar state

machines.

The MachXO2 devices also provide flexible, reliable and secure configuration from on-chip Flash memory. These devices

can also configure themselves from external SPI Flash or be configured by an external master through the JTAG test

access port or through the I2C port. Additionally, MachXO2 devices support dual-boot capability (using external Flash

memory) and remote field upgrade (TransFR) capability.

Lattice provides a variety of design tools that allow complex designs to be efficiently implemented using the MachXO2

family of devices. Popular logic synthesis tools provide synthesis library support for MachXO2. Lattice design tools use the

synthesis tool output along with the user-specified preferences and constraints to place and route the design in the

MachXO2 device. These tools extract the timing from the routing and back-annotate it intothe design for timing

verification.

Lattice provides many pre-engineered IP (Intellectual Property) LatticeCORE™ modules, including a number of reference

designs licensed free of charge, optimized for the MachXO2 PLD family. By using these configurable soft core IP cores as

standardized blocks, users are free to concentrate on the unique aspects of their design, increasing their productivity.

Features

• Flexible Logic Architecture

      Six devices with 256 to 6864 LUT4s and 18 to 334 I/Os

• Ultra Low Power Devices

      Advanced 65 nm low power process

      As low as 22 µW standby power

      Programmable low swing differential I/Os

      Stand-by mode and other power saving options

• Embedded and Distributed Memory

      Up to 240 kbits sysMEM™ Embedded BlockRAM

      Up to 54 kbits Distributed RAM

      Dedicated FIFO control logic

• On-Chip User Flash Memory

      Up to 256 kbits of User Flash Memory

      100,000 write cycles

      Accessible through WISHBONE, SPI, I2C and JTAG interfaces

      Can be used as soft processor PROM or as Flash memory

• Pre-Engineered Source Synchronous I/O

      DDR registers in I/O cells

      Dedicated gearing logic

      7:1 Gearing for Display I/Os

      Generic DDR, DDRX2, DDRX4

      Dedicated DDR/DDR2/LPDDR memory with DQS support

• High Performance, Flexible I/O Buffer

      Programmable sysIO™ buffer supports wide range of interfaces:

      – LVCMOS 3.3/2.5/1.8/1.5/1.2

      – LVTTL

      – PCI

      – LVDS, Bus-LVDS, MLVDS, RSDS, LVPECL

      – SSTL 25/18

      – HSTL 18

      – Schmitt trigger inputs, up to 0.5 V hysteresis

      I/Os support hot socketing

      On-chip differential termination

      Programmable pull-up or pull-down mode

• Flexible On-Chip Clocking

      Eight primary clocks

      Up to two edge clocks for high-speed I/O interfaces (top and bottom sides only)

      Up to two analog PLLs per device with fractional-n frequency synthesis

      – Wide input frequency range (7 MHz to 400 MHz)

• Non-volatile, Infinitely Reconfigurable

      Instant-on – powers up in microseconds

      Single-chip, secure solution

      Programmable through JTAG, SPI or I²C

      Supports background programming of non-vola-tile memory

      Optional dual boot with external SPI memory

• TransFR™ Reconfiguration

      In-field logic update while system operates

• Enhanced System Level Support

      On-chip hardened functions: SPI, I²C, timer/counter

      On-chip oscillator with 5.5% accuracy

      Unique TraceID for system tracking

      One Time Programmable (OTP) mode

      Single power supply with extended operating range

      IEEE Standard 1149.1 boundary scan

      IEEE 1532 compliant in-system programming

• Broad Range of Package Options

      TQFP, WLCSP, ucBGA, csBGA, caBGA, ftBGA, fpBGA, QFN package options

      Small footprint package options

      – As small as 2.5 mm x 2.5 mm

      Density migration supported

      Advanced halogen-free packaging

How to choose FPGA for your project?

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CrossLink™ Field Programmable Gate Array (FPGA) IC 37 184320 5936 80-VFBGA

General Description

CrossLink™ from Lattice Semiconductor is a programmable video bridging device that supports a variety of protocols and

interfaces for mobile image sensors and displays. The device is based on Lattice mobile FPGA 40-nm technology. It

combines the extreme flexibility of an FPGA with the low power, low cost and small footprint of an ASIC.

CrossLink supports video interfaces including MIPI® DPI, MIPI DBI, CMOS camera and display interfaces, OpenLDI,

FPD-Link, FLATLINK, MIPI D-PHY, MIPI CSI-2, MIPI DSI, SLVS200, subLVDS, HiSPi and more.

Lattice Semiconductor provides many pre-engineered IP (Intellectual Property) modules for CrossLink. By using these

configurable soft core IPs as standardized blocks, designers are free to concentrate on the unique aspects of their design,

increasing their productivity.

The Lattice Diamond® design software allows large complex designs to be efficiently implemented using CrossLink.

Synthesis library support for CrossLink devices is available for popular logic synthesis tools. The Diamond tools use the

synthesis tool output along with the constraints from its floor planning tools to place and route the design in the

CrossLink device. The tools extract the timing from the routing and back-annotate it into the design for timing verification.

Interfaces on CrossLink provide a variety of bridging solutions for smart phone, tablets, wearables, VR, AR, Drone, Smart

Home, HMI as well as adjacent ISM markets. The device is capable of supporting high-resolution, high-bandwidth content

for mobile cameras and displays at 4 UHD and beyond.

Features

• Ultra-low power

• Sleep Mode Support

• Normal Operation – From 5 mW to 150 mW

• Ultra small footprint packages

      36-ball WLCSP (6 mm2)

      64-ball ucfBGA (12 mm2)

      80-ball ctfBGA (42 mm2)

      80-ball ckfBGA (49 mm2)

      81-ball csfBGA (20 mm2)

• Programmable architecture

      5936 LUTs

      180 Kb block RAM

      47 Kb distributed RAM

• Two hardened 4-lane MIPI D-PHY interfaces

      Transmit and receive

      6 Gb/s per D-PHY interface

• Programmable source synchronous I/O

      MIPI D-PHY Rx, LVDS Rx, LVDS Tx, subLVDS Rx, SLVS200 Rx, HiSPi Rx

      Up to 1200 Mb/s per I/O

      Four high-speed clock inputs

• Programmable CMOS I/O

      LVTTL and LVCMOS

      3.3 V, 2.5 V, 1.8 V and 1.2 V (outputs)

      LVCMOS differential outputs

• Flexible device configuration

      One Time Programmable (OTP) non-volatile configuration memory

      Master SPI boot from external flash

      Dual image booting supported

      I2C programming

      SPI programming

      TransFR™ I/O for simple field updates

• Enhanced system level support

      Reveal logic analyzer

      TraceID for system tracking

      On-chip hardened I2C block

• Applications examples

      Dual MIPI CSI-2 to Single MIPI CSI-2 Aggregation

      Quad MIPI CSI-2 to Single MIPI CSI-2 Aggregation

      Single MIPI DSI to Single MIPI DSI Repeater

      Single MIPI CSI-2 to Single MIPI CSI-2 Repeater

      Single MIPI DSI to Dual MIPI DSI Splitter

      Single MIPI CSI-2 to Dual MIPI CSI-2 Splitter

      MIPI DSI to OpenLDI/FPD-Link/LVDS Translator

      OpenLDI/FPD-Link/LVDS to MIPI DSI Translator

      MIPI DSI/CSI-2 to CMOS Translator

      CMOS to MIPI DSI/CSI-2 Translator

      subLVDS to MIPI CSI-2 Translator

How to choose FPGA for your project?

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XP2 Field Programmable Gate Array (FPGA) IC 201 396288 29000 256-LBGA

General Description

LatticeXP2 devices combine a Look-up Table (LUT) based FPGA fabric with non-volatile Flash cells in an architecture

referred to as flexiFLASH.

The flexiFLASH approach provides benefits including instant-on, infinite reconfigurability, on chip storage with FlashBAK

embedded block memory and Serial TAG memory and design security. The parts also support Live Update technology with

TransFR, 128-bit AES Encryption and Dual-boot technologies.

The LatticeXP2 FPGA fabric was optimized for the new technology from the outset with high performance and low cost in

mind. LatticeXP2 devices include LUT-based logic, distributed and embedded memory, Phase Locked Loops (PLLs),

pre-engineered source synchronous I/O support and enhanced sysDSP blocks.

Lattice Diamond® design software allows large and complex designs to be efficiently implemented using the LatticeXP2

family of FPGA devices. Synthesis library support for LatticeXP2 is available for popular logic synthesis tools. The Diamond

software uses the synthesis tool output along with the constraints from its floor planning tools to place and route the

design in the LatticeXP2 device. The Diamond tool extracts the timing from the routing and back-annotates it into the

design for timing verification.

Lattice provides many pre-designed Intellectual Property (IP) LatticeCORE™ modules for the LatticeXP2 family. By using

these IPs as standardized blocks, designers are free to concentrate on the unique aspects of their design, increasing their

productivity.

Features

• flexiFLASH™ Architecture

      Instant-on

      Infinitely reconfigurable

      Single chip

      FlashBAK™ technology

      Serial TAG memory

      Design security

• Live Update Technology

      TransFR™ technology

      Secure updates with 128 bit AES encryption

      Dual-boot with external SPI

• sysDSP™ Block

      Three to eight blocks for high performance Multiply and Accumulate

      12 to 32 18x18 multipliers

      Each block supports one 36x36 multiplier or four 18x18 or eight 9x9 multipliers

• Embedded and Distributed Memory

      Up to 885 Kbits sysMEM™ EBR

      Up to 83 Kbits Distributed RAM

• sysCLOCK™ PLLs

      Up to four analog PLLs per device

      Clock multiply, divide and phase shifting

• Flexible I/O Buffer

      sysIO™ buffer supports:

            – LVCMOS 33/25/18/15/12; LVTTL

            – SSTL 33/25/18 class I, II

            – HSTL15 class I; HSTL18 class I, II

            – PCI

            – LVDS, Bus-LVDS, MLVDS, LVPECL, RSDS

• Pre-engineered Source SynchronousInterfaces

      DDR / DDR2 interfaces up to 200 MHz

      7:1 LVDS interfaces support display applications

      XGMII

• Density And Package Options

      5k to 40k LUT4s, 86 to 540 I/Os

      csBGA, TQFP, PQFP, ftBGA and fpBGA packages

      Density migration supported

• Flexible Device Configuration

      SPI (master and slave) Boot Flash Interface

      Dual Boot Image supported

      Soft Error Detect (SED) macro embedded

• System Level Support

      IEEE 1149.1 and IEEE 1532 Compliant

      On-chip oscillator for initialization & general use

      Devices operate with 1.2V power supply

How to choose FPGA for your project?

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