Microsemi Corporation

IGLOO nano Field Programmable Gate Array (FPGA) IC 49 768 68-VFQFN Exposed Pad

General Description

The IGLOO family of flash FPGAs, based on a 130-nm flash process, offers the lowest power FPGA, a single-chip solution,

small footprint packages, reprogrammability, and an abundance of advanced features.

The Flash*Freeze technology used in IGLOO nano devices enables entering and exiting an ultra-low power mode that

consumes nanoPower while retaining SRAM and register data. Flash*Freeze technology simplifies power management

through l/O and clock management with rapid recovery to operation mode.

The Low Power Active capability (static idle) allows for ultra-low power consumption while the IGLOO nano device is

completely functional in the system. This allows the IGLO0 nano device to control system power management based on

external inputs (e.g., scanning for keyboard stimulus) while consuming minimal power.

Nonvolatile flash technology gives lGLOO nano devices the advantage of being a secure, low power, single-chip solution

that is Instant On. The IGLOO nano device is reprogrammable and offers time-to-market benefits at an ASIC-level unit

cost.

These features enable designers to create high-density systems using existing ASIC or FPGA design flows and tools.

IGLOO nano devices offer 1 kbit of on-chip, reprogrammable, nonvolatile FlashROM storage as well as clock conditioning

circuitry based on an integrated phase-locked loop (PLL). The AGLN030 and smaller devices have no PLL or RAM support.

IGLOO nano devices have up to 250 k system gates, supported with up to 36 kbits of true dual-port SRAM and up to 71

user l/Os.

IGLOO nano devices increase the breadth of the IGLOO product line by adding new features and packages for greater

customer value in high volume consumer, portable, and battery-backed markets. Features such as smaller footprint

packages designed with two-layer PCBs in mind, power consumption measured in nanoPower, Schmitt trigger, and bus

hold (hold previous l/O state in Flash*Freeze mode) functionality make these devices ideal for deployment in applications

that require high levels of flexibility and low cost.

Features and Benefits

• Low Power

      nanoPower Consumption-Industry's Lowest Power

      1.2 V to 1.5 V Core Voltage Support for Low Power

      Supports Single-Voltage System Operation

      Low Power Active FPGA Operation

      Flash*Freeze Technology Enables Ultra-Low Power Consumption while MaintainingFPGA Content

      Easy Entry to / Exit from Ultra-Low Power Flash*Freeze Mode

• Small Footprint Packages

      As Small as 3x3 mm in Size

• Wide Range of Features

      10,000 to 250,000 System Gates

      Up to 36 kbits of True Dual-Port SRAM

      Up to 71 User 1/Os

• Reprogrammable Flash Technology

      130-nm, 7-Layer Metal, Flash-Based CMOS Process

      Instant On Level 0 Support

      Single-Chip Solution

      Retains Programmed Design When Powered Off

      250 MHz (1.5 V systems) and 160 MHz (1.2 V systems) System Performance

• In-System Programming (ISP) and Security

      ISP Using On-Chip 128-BitAdvanced Encryption Standard (AES) Decryption via JTAG (IEEE 1532-compliant)

      FlashLock®Designed to Secure FPGA Contents

      1.2 V Programming

• High-Performance Routing Hierarchy

      Segmented,Hierarchical Routing and Clock Structure

• Advanced I/Os

      1.2 V, 1.5 V, 1.8 V, 2.5 V,and 3.3 V Mixed-Voltage Operation

      Bank-Selectable I/O Voltages-up to 4 Banks per Chip

      Single-Ended I/O Standards:LVTTL,LVCMOS 3.3V/2.5 V/ 1.8 V/1.5 V/1.2V

      Wide Range Power Supply Voltage Support per JESD8-B, Allowing I/Os to Operate from 2.7 V to 3.6V

      Wide Range Power Supply Voltage Support per JESD8-12, Allowing I/Os to Operate from 1.14 V to 1.575V

      I/O Registers on Input, Output, and Enable Paths

      Selectable Schmitt Trigger Inputs

      Hot-Swappable and Cold-Sparing I/Os

      Programmable Output Slew Rate and Drive Strength

      Weak Pull-Up/-Down

      IEEE 1149.1(JTAG) Boundary Scan Test

      Pin-Compatible Packages across the IGLOO®Family

• Clock Conditioning Circuit(CCC) and PLLt

      Up to Six CCC Blocks, One with an Integrated PLL

      Configurable Phase Shift, Multiply/Divide, Delay Capabilities, and External Feedback

      Wide Input Frequency Range (1.5 MHz up to 250 MHz)

• Embedded Memory

      1 kbit of FlashROM User Nonvolatile Memory

      SRAMs and FIFOs with Variable-Aspect-Ratio4,608-Bit RAM Blocks (x1, x2, x4, x9, and x18 organizations)

      True Dual-Port SRAM(except x18 organization)

• Enhanced Commercial Temperature Range

      Tj=-20℃ to +85℃

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IGLOO Field Programmable Gate Array (FPGA) IC 97 55296 9216 144-LBGA

General Description

The IGLOO family of flash FPGAs, based on a 130-nm flash process, offers the lowest power FPGA, a single-chip solution,

small footprint packages, reprogrammability, and an abundance of advanced features.

The Flash*Freeze technology used in IGLOO devices enables entering and exiting an ultra-low power mode that

consumes as little as 5 μW while retaining SRAM and register data. Flash*Freeze technology simplifies power management

through I/O and clock management with rapid recovery to operation mode.

The Low Power Active capability (static idle) allows for ultra-low power consumption (from 12 μW) while the IGLOO device

is completely functional in the system. This allows the IGLOO device to control system power management based on

external inputs (e.g., scanning for keyboard stimulus) while consuming minimal power.

Nonvolatile flash technology gives IGLOO devices the advantage of being a secure, low power, single-chip solution that is

Instant On. IGLOO is reprogrammable and offers time-to-market benefits at an ASIC-level unit cost.

These features enable designers to create high-density systems using existing ASIC or FPGA design flows and tools.

IGLOO devices offer 1 kbit of on-chip, reprogrammable, nonvolatile FlashROM storage as well as clock conditioning

circuitry based on an integrated phase-locked loop (PLL). The AGL015 and AGL030 devices have no PLL or RAM support.

IGLOO devices have up to 1 million system gates, supported with up to 144 kbits of true dual-port SRAM and up to 300

user I/Os.

M1 IGLOO devices support the high-performance, 32-bit Cortex-M1 processor developed by ARM for implementation in

FPGAs. Cortex-M1 is a soft processor that is fully implemented in the FPGA fabric. It has a three-stage pipeline that offers

a good balance between low power consumption and speed when implemented in an M1 IGLOO device. The processor

runs the ARMv6-M instruction set, has a configurable nested interrupt controller, and can be implemented with or

without the debug block. Cortex-M1 is available for free from Microsemi for use in M1 IGLOO FPGAs.

The ARM-enabled devices have ordering numbers that begin with M1AGL and do not support AES decryption.

Features and Benefits

• Low Power

      1.2 V to 1.5 V Core Voltage Support for Low Power

      Supports Single-Voltage System Operation

      5 μW Power Consumption in Flash*Freeze Mode

      Low Power Active FPGA Operation

      Flash*Freeze Technology Enables Ultra-Low Power Consumption while MaintainingFPGA Content

      Easy Entry to / Exit from Ultra-Low Power Flash*Freeze Mode

• High Capacity

      15K to 1 Million System Gates

      Up to 144 Kbits of True Dual-Port SRAM

      Up to 300 User 1/Os

• Reprogrammable Flash Technology

      130-nm, 7-Layer Metal, Flash-Based CMOS Process

      Instant On Level 0 Support

      Single-Chip Solution

      Retains Programmed Design When Powered Off

      250 MHz (1.5 V systems) and 160 MHz (1.2 V systems) System Performance

• In-System Programming (ISP) and Security

      ISP Using On-Chip 128-Bit Advanced Encryption Standard (AES) Decryption (except ARM®-enabled IGLOO®devices)

      via JTAG (IEEE 1532-compliant)

      FlashLock®Designed to Secure FPGA Contents

• High-Performance Routing Hierarchy

      Segmented, Hierarchical Routing and Clock Structure

• Advanced l/O

      700 Mbps DDR,LVDS-Capable I/Os (AGL250 and above)

      1.2 V, 1.5 V, 1.8 V, 2.5V, and 3.3 V Mixed-Voltage Operation

      Bank-Selectable I/O Voltages--up to 4 Banks per Chip

      Single-Ended I/O Standards:LVTTL,LVCMOS 3.3V/2.5 V/ 1.8 V /1.5 V/ 1.2 .V, 3.3 V PCI/ 3.3 V PCI-X, and LVCMOS

      2.5 V/5.0V Input

      DifferentialI/O Standards:LVPECL，LVDS，B-LVDS,and M-LVDS (AGL250 and above)

      Wide Range Power Supply Voltage Support per JESD8-B, Allowing I/Os to Operate from 2.7 V to 3.6 V

      Wide Range Power Supply Voltage Support per JESD8-12, Allowing I/Os to Operate from 1.14 V to 1.575V

      I/O Registers on Input, Output, and Enable Paths

      Hot-Swappable and Cold-Sparing,I/Os+

      Programmable Output Slew Rateand Drive Strength

      Weak Pull-Up/-Down

      IEEE 1149.1 (JTAG) Boundary Scan Test

      Pin-Compatible Packages across the IGLOO Family

• Clock Conditioning Circuit(CCC) and PLL

      Six CCC Blocks, One with an Integrated PLL

      Configurable Phase Shift, Multiply/Divide,Delay Capabilities, and External Feedback

      Wide Input Frequency Range (1.5 MHz up to 250 MHz)

• Embedded Memory

      1 kbit of FlashROM User Nonvolatile Memory

      SRAMs and FIFOs with Variable-Aspect-Ratio4,608-Bit RAM Blocks (x1,x2,x4, x9, and x18 organizations)

      True Dual-Port SRAM (except x18)

• ARM Processor Support in IGLOO FPGAs

      M1 IGLOO Devices--Cortex®-M1 Soft Processor Available with or without Debug

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ProASIC3 Field Programmable Gate Array (FPGA) IC 80 18432 132-WFQFN

General Description

ProASIC3，the third-generation family of Microsemi flash FPGAs, offers performance, density, and features beyond those

of the ProASIC^PLUS® family. Nonvolatile flash technology gives ProASIC3 devices the advantage of being a secure, low

power, single-chip solution that is Instant On. ProASIC3 is reprogrammable and offers time-to-market benefits at an

ASIC-level unit cost. These features enable designers to create high-density systems using existing ASIC or FPGA design

flows and tools.

ProASIC3 devices offer 1 kbit of on-chip, reprogrammable, nonvolatile FlashROM storage as well as clock conditioning

circuitry based on an integrated phase-locked loop (PLL). The A3P015 and A3P030 devices have no PLL or RAM support.

ProASIC3 devices have up to 1 million system gates, supported with up to 144 kbits of true dual-port SRAM and up to

300 user I/Os.

ProASIC3 devices support the ARM Cortex-M1 processor. The ARM-enabled devices have Microsemi ordering numbers

that begin with M1A3P (Cortex-M1) and do not support AES decryption.

Features and Benefits

• High Capacity

      15 K to 1 M System Gates

      Up to 144 Kbits of True Dual-Port SRAM

      Up to 300 User I/Os

• Reprogrammable Flash Technology

      130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Process

      Instant On Level 0 Support

      Single-Chip Solution

      Retains Programmed Design when Powered Off

• High Performance

      350 MHz System Performance

      3.3 V, 66 MHz 64-Bit PCI

• In-System Programming (ISP) and Security

      ISP Using On-Chip 128-Bit Advanced Encryption Standard (AES) Decryption (except ARM®-enabled ProASIC®3

      devices) via JTAG (IEEE 1532-compliant)

      FlashLock® to Secure FPGA Contents

• Low Power

      Core Voltage for Low Power

      Support for 1.5V-Only Systems

      Low-Impedance Flash Switches

• High-Performance Routing Hierarchy

      Segmented, Hierarchical Routing and Clock Structure

• Advanced I/O

      700 Mbps DDR,LVDS-Capable I/Os (A3P250 and above)

      1.5V, 1.8 V, 2.5 V,and 3.3V Mixed-Voltage Operation

      Wide Range Power Supply Voltage Support per JESD8-B, Allowing I/Os to Operate from 2.7 V to 3.6 V

      Bank-Selectable I/O Voltages—up to 4 Banks per Chip

      Single-Ended I/O Standards: LVTTL, LVCMOS 3.3V / 2.5V / 1.8V / 1.5V, 3.3V PCI / 3.3V PCI-X and LVCMOS 2.5V / 5.0V

      Input

      Differential I/O Standards: LVPECL，LVDS，B-LVDS, and M-LVDS (A3P250 and above)

      I/O Registers on Input, Output, and Enable Paths

      Hot-Swappable and Cold Sparing I/Os

      Programmable Output Slew Rate and Drive Strength

      Weak Pull-Up/-Down

      IEEE 1149.1 (JTAG) Boundary Scan Test

      Pin-Compatible Packages across the ProASIC3 Family

• Clock Conditioning Circuit (CCC) and PLL

      Six CCC Blocks, One with an Integrated PLL

      Configurable Phase-Shift, Multiply/Divide, Delay Capabilities and External Feedback

      Wide Input Frequency Range (1.5 MHz to 350 MHz)

• Embedded Memory

      1 Kbit of FlashROM User Nonvolatile Memory

      SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM Blocks (x1, x2, x4, x9, and x18 organizations)

      True Dual-Port SRAM (except x18)

• ARM Processor Support in ProASIC3 FPGAs

      M1 ProASIC3 Devices-ARM®Cortex®-M1 Soft Processor Available with or without Debug

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ProASIC3L Field Programmable Gate Array (FPGA) IC 68 36864 100-TQFP

Clock Frequency Synthesis

Deriving clocks of various frequencies from a single reference clock is known as frequency synthesis.The PLL has an input

frequency range from 1.5 to 350 MHz. This frequency is automatically divideddown to a range between 1.5 MHz and

5.5 MHz by input dividers (not shown in Figure 4-19 on page 100)between PLL macro inputs and PLL phase detector

inputs. The VCO output is capable of an outputrange from 24 to 350 MHz. With dividers before the input to the PLL core

and following the VCO outputs,the VCO output frequency can be divided to provide the final frequency range from 0.75

to 350 MHz.Using SmartGen, the dividers are automatically set to achieve the closest possible matches to thespecified

output frequencies.

Users should be cautious when selecting the desired PLL input and output frequencies and the I/O bufferstandard used

to connect to the PLL input and output clocks. Depending on the I/O standards used forthe PLL input and output clocks,

the I/O frequencies have different maximum limits. Refer to the familydatasheets for specifications of maximum I/O

frequencies for supported I/O standards. Desired PLL inputor output frequencies will not be achieved if the selected

frequencies are higher than the maximum I/Ofrequencies allowed by the selected I/O standards. Users should be careful

when selecting the I/Ostandards used for PLL input and output clocks. Performing post-layout simulation can help detect

thistype of error, which will be identified with pulse width violation errors. Users are strongly encouraged toperform

post-layout simulation to ensure the I/O standard used can provide the desired PLL input oroutput frequencies. Users can

also choose to cascade PLLs together to achieve the high frequenciesneeded for their applications. Details of cascading

PLLs are discussed in the "Cascading CCCs" sectionon page 125.

In SmartGen, the actual generated frequency (under typical operating conditions) will be displayedbeside the requested

output frequency value. This provides the ability to determine the exact frequencythat can be generated by SmartGen, in

real time. The log file generated by SmartGen is a useful tool indetermining how closely the requested clock frequencies

match the user specifications. For example,assume a user specifies 101 MHz as one of the secondary output frequencies.

If the best outputfrequency that could be achieved were 100 MHz, the log file generated by SmartGen would indicate

theactual generated frequency

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