NXP Semiconductors

56800 56F805 Microcontroller IC 16-Bit 80MHz 64KB (32K x 16) FLASH 144-LQFP (20x20)

56F805 Description

The 56F805 is a member of the 56800 core-based family of processors. It combines, on a single chip, the

processing power of a DSP and the functionality of a microcontroller with a flexible set of peripherals to

create an extremely cost-effective solution. Because of its low cost, configuration flexibility, and compact

program code, the 56F805 is well-suited for many applications. The 56F805 includes many peripherals

that are especially useful for applications such as motion control, smart appliances, steppers, encoders,

tachometers, limit switches, power supply and control, automotive control, engine management, noise

suppression, remote utility metering, and industrial control for power, lighting, and automation.

The 56800 core is based on a Harvard-style architecture consisting of three execution units operating in

parallel, allowing as many as six operations per instruction cycle. The microprocessor-style programming

model and optimized instruction set allow straightforward generation of efficient, compact code for both

MCU and DSP applications. The instruction set is also highly efficient for C compilers to enable rapid

development of optimized control applications.

The 56F805 supports program execution from either internal or external memories. Two data operands can

be accessed from the on-chip Data RAM per instruction cycle. The 56F805 also provides two external

dedicated interrupt lines, and up to 32 General Purpose Input/Output (GPIO) lines, depending on

peripheral configuration.

The 56F805 controller includes 31.5K words (16-bit) of Program Flash and 4K words of Data Flash (each

programmable through the JTAG port) with 512 words of Program RAM and 2K words of Data RAM. It

also supports program execution from external memory (64K).

The 56F805 incorporates a total of 2K words of Boot Flash for easy customer-inclusion of

field-programmable software routines that can be used to program the main Program and Data Flash

memory areas. Both Program and Data Flash memories can be independently bulk-erased or erased in page

sizes of 256 words. The Boot Flash memory can also be either bulk- or page-erased.

Key application-specific features of the 56F805 include the two Pulse Width Modulator (PWM) modules.

These modules each incorporate three complementary, individually programmable PWM signal outputs

(each module is also capable of supporting six independent PWM functions for a total of 12 PWM outputs)

to enhance motor control functionality. Complementary operation permits programmable dead time

insertion, distortion correction via current sensing by software, and separate top and bottom output polarity

control. The up-counter value is programmable to support a continuously variable PWM frequency. Edgeand

center-aligned synchronous pulse width control (0% to 100% modulation) is supported. The device is

capable of controlling most motor types: ACIM (AC Induction Motors), both BDC and BLDC (Brush and

Brushless DC motors), SRM and VRM (Switched and Variable Reluctance Motors), and stepper motors.

The PWMs incorporate fault protection and cycle-by-cycle current limiting with sufficient output drive

capability to directly drive standard opto-isolators. A “smoke-inhibit”, write-once protection feature for

key parameters and a patented PWM waveform distortion correction circuit are also provided. Each PWM

is double-buffered and includes interrupt controls to permit integral reload rates to be programmable from

1 to 16. The PWM modules provide a reference output to synchronize the ADCs.

The 56F805 incorporates two separate Quadrature Decoders capable of capturing all four transitions on

the two-phase inputs, permitting generation of a number proportional to actual position. Speed

computation capabilities accommodate both fast and slow moving shafts. The integrated watchdog timer

in the Quadrature Decoder can be programmed with a time-out value to alarm when no shaft motion is

detected. Each input is filtered to ensure only true transitions are recorded.

This controller also provides a full set of standard programmable peripherals that include two Serial

Communications Interfaces (SCI), one Serial Peripheral Interface (SPI), and four Quad Timers. Any of

these interfaces can be used as General Purpose Input/Outputs (GPIOs) if that function is not required. A

Controller Area Network interface (CAN Version 2.0 A/B-compliant), an internal interrupt controller and

14 dedicated GPIO are also included on the 56F805.

56F805 Features

1.1.1 Processing Core

• Efficient 16-bit 56800 family processor engine with dual Harvard architecture

• As many as 40 Million Instructions Per Second (MIPS) at 80MHz core frequency

• Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC)

• Two 36-bit accumulators, including extension bits

• 16-bit bidirectional barrel shifter

• Parallel instruction set with unique processor addressing modes

• Hardware DO and REP loops

• Three internal address buses and one external address bus

• Four internal data buses and one external data bus

• Instruction set supports both DSP and controller functions

• Controller style addressing modes and instructions for compact code

• Efficient C compiler and local variable support

• Software subroutine and interrupt stack with depth limited only by memory

• JTAG/OnCE debug programming interface

1.1.2 Memory

• Harvard architecture permits as many as three simultaneous accesses to Program and Data memory

• On-chip memory including a low-cost, high-volume Flash solution

— 31.5K × 16 bit words of Program Flash

— 512 × 16-bit words of Program RAM

— 4K× 16-bit words of Data Flash

— 2K × 16-bit words of Data RAM

— 2K × 16-bit words of Boot Flash

• Off-chip memory expansion capabilities programmable for 0, 4, 8, or 12 wait states

— As much as 64K × 16 bits of Data memory

— As much as 64K × 16 bits of Program memory

1.1.3 Peripheral Circuits for 56F805

• Two Pulse Width Modulator modules each with six PWM outputs, three Current Sense inputs, and four

Fault inputs, fault tolerant design with dead time insertion; supports both center- and edge-aligned modes

• Two 12-bit Analog-to-Digital Converters (ADC) which support two simultaneous conversions; ADC and

PWM modules can be synchronized

• Two General Purpose Quad Timers totaling six pins: Timer C with two pins and Timer D with four pins

• CAN 2.0 B Module with 2-pin port for transmit and receive

• Two Serial Communication Interfaces, each with two pins (or four additional GPIO lines)

• Serial Peripheral Interface (SPI) with configurable four-pin port (or four additional GPIO lines)

• 14 dedicated General Purpose I/O (GPIO) pins, 18 multiplexed GPIO pins

• Computer Operating Properly (COP) watchdog timer

• Two dedicated external interrupt pins

• External reset input pin for hardware reset

• External reset output pin for system reset

• JTAG/On-Chip Emulation (OnCE™) module for unobtrusive, processor speed-independent debugging

• Software-programmable, Phase Locked Loop-based frequency synthesizer for the controller core clock

1.1.4 Energy Information

• Fabricated in high-density CMOS with 5V-tolerant, TTL-compatible digital inputs

• Uses a single 3.3V power supply

• On-chip regulators for digital and analog circuitry to lower cost and reduce noise

• Wait and Stop modes available

• Two Quadrature Decoders each with four inputs or two additional Quad Timers

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