NXP USA Inc.

XA XA Microcontroller IC 16-Bit 32MHz 32KB (32K x 8) OTP 44-LQFP (10x10)

GENERAL DESCRIPTION

The XA–C3 is a member of the Philips XA (eXtended Architecture) family of high–performance 16–bit single–chip microcontrollers. The

XA–C3 combines an array of standard peripherals together with a PeliCAN CAN 2.0B engine and unique ”Message Management”

hardware to provide integrated support for most CAN Transport Layer (CTL) protocols such as DeviceNet, CANopen and OSEK. For

additional details, refer to the XA-C3 Overview on page 35.

The XA architecture supports:

•Easy 16-bit migration from the 80C51 architecture.

•16–bit fully static CPU with 24–bit addressed PROGRAM and DATA spaces.

•Twenty–one 16–bit CPU core registers capable of all arithmetic and logic operations while serving as memory pointers.

•An enhanced orthogonal instruction set tailored for high–level support of the C language.

•Multi–tasking and direct real–time executive support.

•Low–power operation intrinsic to the XA architecture includes Power–Down and Idle modes.

FEATURES IN COMMON WITH XA-G3

•Pin–compatibility (CAN RxD and CAN TxD use the XA-G3 NC pins).

•32K bytes of on–chip EPROM PROGRAM memory (see Table 1).

•44–pin PLCC (Figure 1 and Table 2) and 44–pin LQFP (Figure 2 and Table 3) packages.

•Commercial (0 to 70oC) and Industrial (–40 to 85oC) ranges.

•Supports off–chip addressing of PROGRAM and DATA memory up to 1 megabyte each (20 address lines).

•Three standard counter/timers (T0, T1, and T2) with enhancements such as Auto Reload for PWM outputs.

•UART–0 with enhancements such as separate Rx and Tx interrupts, Break Detection, and Automatic Address Recognition.

•Watchdog with a secure WFEED1 / WFEED2 sequence.

•Four 8–bit I/O ports with 4 programmable output configurations per pin.

XA-C3 SPECIFIC FEATURES

•32 MHz operating frequency at 4.5 to 5.5V operation.

•One Serial Port Interface (SPI)

•1024 bytes of on–chip DATA RAM.

•42 vectored interrupts. These include 13 maskable Events, 7 Software interrupts, 6 Exceptions, 16 software Traps, segmented

DATA memory, multiple User stacks, and banked registers to support rapid context switching.

•External interfacing via a 16–bit DATA bus width. 

XA-C3 CAN AND CTL FEATURES

•A PeliCAN CAN 2.0B engine from the SJA1000 Stand–alone CAN controller which supports 11– and 29–bit IDentifiers and the

maximum CAN data rate (1 Mbps) and CAN Diagnostics.

•Hardware “Message Management” support for all major CTL protocols: DeviceNet, CANopen, OSEK.

•Automatic (hardware) assembly of Fragmented Messages via a Transport Layer Co-Processor. Concurrent assembly of up to 32

separate interleaved Fragmented Messages

•32 CAN Transport Layer (CTL) Message Objects are modelled as a FullCAN Object Superset.

•32 separate filters/screeners (one per Message Object), each allowing a 30–bit ID Match and full 29–bit Mask (i.e., each

filter/screener represents a unique Group address).

•Each Message Object can be configured as Receive or Transmit.

•A separate message buffer is associated with each CTL Message Object. 32 message buffers are located in XRAM and managed

by 32 DMA channels. Message buffer size for each Message Object is independently configurable in length (from 2 to 256

bytes).

•For single–chip systems there is a 512–byte (on–chip) XRAM message buffer, independent of the 1K on–chip DATA RAM, which

is extendable (off–chip) to 8K bytes (i.e., 32 Message Objects that can be up to 256 bytes each).