NXP USA Inc.

S12Z S12 MagniV Microcontroller IC 16-Bit 40MHz 32KB (32K x 8) FLASH 48-LQFP-EP (7x7)

Introduction

The MC9S12ZVM-Family is an automotive 16-bit microcontroller family using the NVM + UHV

technology that offers the capability to integrate 40 V analog components. This family reuses many

features from the existing S12/S12X portfolio. The particular differentiating features of this family are the

enhanced S12Z core, the combination of dual-ADC synchronized with PWM generation and the

integration of “high-voltage” analog modules, including the voltage regulator (VREG), Gate Drive Unit

(GDU) and a Local Interconnect Network (LIN) physical layer. These features enable a fully integrated

single chip solution to drive up to 6 external power MOSFETs for BLDC or PMSM motor drive

applications.

The MC9S12ZVM-Family includes error correction code (ECC) on RAM and flash memory, EEPROM

for diagnostic or data storage, a fast analog-to-digital converter (ADC) and a frequency modulated phase

locked loop (IPLL) that improves the EMC performance. The MC9S12ZVM-Family delivers an

optimized solution with the integration of several key system components into a single device, optimizing

system architecture and achieving significant space savings. The MC9S12ZVM-Family delivers all the

advantages and efficiencies of a 16-bit MCU while retaining the low cost, power consumption, EMC, and

code-size efficiency advantages currently enjoyed by users of existing S12(X) families. The

MC9S12ZVM-Family is available in different pin-out options, using the 64-pin LQFP-EP and 48-pin

LQFP-EP packages to accommodate LIN, CAN and external PWM based application interfaces. In

addition to the I/O ports available in each module, further I/O ports are available with interrupt capability

allowing wake-up from stop or wait modes.

The MC9S12ZVM-Family is a general-purpose family of devices suitable for a range of applications,

including:

• 3-phase sensorless BLDC motor control for

— Fuel pump

— Water pump

— Oil pump

— A/C compressor

— HVAC blower

— Engine cooling fan

— Electric vehicle battery cooling fan

• Brush DC motor control requiring driving in 2 directions, along with PWM control for

— Reversible wiper

— Trunk opener

Chip-Level Features

On-chip modules available within the family include the following features:

• S12Z CPU core

• 128, 64, 32 or 16KB on-chip flash with ECC

• 512 or128 byte EEPROM with ECC

• 8, 4 or 2 KB on-chip SRAM with ECC

• Phase locked loop (IPLL) frequency multiplier with internal filter

• 1 MHz internal RC oscillator with +/-1.3% accuracy over rated temperature range

• 4-20MHz amplitude controlled pierce oscillator

• Internal COP (watchdog) module

• 6-channel, 15-bit pulse width modulator with fault protection (PMF) 

• Low side and high side FET pre-drivers for each phase

— Gate drive pre-regulator

— LDO (Low Dropout Voltage Regulator) (typically 11V)

— High side gate supply generated using bootstrap circuit with external diode and capacitor

— Sustaining charge pump with two external capacitors and diodes

— High side drain (HD) monitoring on internal ADC channel using HD/5 voltage

• Two parallel analog-to-digital converters (ADC) with 12-bit resolution and up to 9 channels

available on external pins

• Programmable Trigger Unit (PTU) for synchronization of PMF and ADC

• One serial peripheral interface (SPI) module

• One serial communication interface (SCI) module with interface to internal LIN physical layer

transceiver (with RX connected to a timer channel for frequency calibration purposes, if desired)

• Up to one additional SCI (not connected to LIN physical layer)

• On-chip LIN physical layer transceiver fully compliant with the LIN 2.2 standard

(S12ZVML versions)

• One High Voltage physical interface. (S12ZVM32, S12ZVM16 versions only)

• 4-channel timer module (TIM) with input capture/output compare

• MSCAN (1 Mbit/s, CAN 2.0 A, B software compatible) module

• On-chip voltage regulator (VREG) for regulation of input supply and all internal voltages

— Optional VREG ballast control output to supply an external CAN physical layer

• Two current sense circuits for overcurrent detection or torque measurement

• Autonomous periodic interrupt (API)

• 20mA high-current output for use as Hall sensor supply

• Supply voltage sense with low battery warning

• Chip temperature sensor

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S12 HCS12 Microcontroller IC 16-bit 25MHz 48KB(48K x 8) Flash 64-LQFP(10x10)

Introduction

The MC9S12G-Family is an optimized, automotive, 16-bit microcontroller product line focused on

low-cost, high-performance, and low pin-count. This family is intended to bridge between high-end 8-bit

microcontrollers and high-performance 16-bit microcontrollers, such as the MC9S12XS-Family. The

MC9S12G-Family is targeted at generic automotive applications requiring CAN or LIN/J2602

communication. Typical examples of these applications include body controllers, occupant detection, door

modules, seat controllers, RKE receivers, smart actuators, lighting modules, and smart junction boxes.

The MC9S12G-Family uses many of the same features found on the MC9S12XS- and MC9S12P-Family,

including error correction code (ECC) on flash memory, a fast analog-to-digital converter (ADC) and a

frequency modulated phase locked loop (IPLL) that improves the EMC performance. 

The MC9S12G-Family is optimized for lower program memory sizes down to 16k. In order to simplify

customer use it features an EEPROM with a small 4 bytes erase sector size.

The MC9S12G-Family deliver all the advantages and efficiencies of a 16-bit MCU while retaining the low

cost, power consumption, EMC, and code-size efficiency advantages currently enjoyed by users of NXP’s

existing 8-bit and 16-bit MCU families. Like the MC9S12XS-Family, the MC9S12G-Family run 16-bit

wide accesses without wait states for all peripherals and memories. The MC9S12G-Family is available in

100-pin LQFP, 64-pin LQFP, 48-pin LQFP/QFN, 32-pin LQFP and 20-pin TSSOP package options and

aims to maximize the amount of functionality especially for the lower pin count packages. In addition to

the I/O ports available in each module, further I/O ports are available with interrupt capability allowing

wake-up from stop or wait modes.

Chip-Level Features

On-chip modules available within the family include the following features:

• S12 CPU core

• Up to 240 Kbyte on-chip flash with ECC

• Up to 4 Kbyte EEPROM with ECC

• Up to 11 Kbyte on-chip SRAM

• Phase locked loop (IPLL) frequency multiplier with internal filter

• 4–16 MHz amplitude controlled Pierce oscillator

• 1 MHz internal RC oscillator

• Timer module (TIM) supporting up to eight channels that provide a range of 16-bit input capture,

output compare, counter, and pulse accumulator functions

• Pulse width modulation (PWM) module with up to eight x 8-bit channels

• Up to 16-channel, 10 or 12-bit resolution successive approximation analog-to-digital converter

(ADC)

• Up to two 8-bit digital-to-analog converters (DAC)

• Up to one 5V analog comparator (ACMP)

• Up to three serial peripheral interface (SPI) modules

• Up to three serial communication interface (SCI) modules supporting LIN communications

• Up to one multi-scalable controller area network (MSCAN) module (supporting CAN protocol

2.0A/B)

• On-chip voltage regulator (VREG) for regulation of input supply and all internal voltages

• Autonomous periodic interrupt (API)

• Precision fixed voltage reference for ADC conversions

• Optional reference voltage attenuator module to increase ADC accuracy

56800E 56F8xxx Microcontroller IC 16-Bit 40MHz 128KB (64K x 16) FLASH 128-LQFP (14x20)

Device Description

The 56F8345 and 56F8145 are members of the 56800E core-based family of controllers. Each combines,

on a single chip, the processing power of a Digital Signal Processor (DSP) and the functionality of a

microcontroller with a flexible set of peripherals to create an extremely cost-effective solution. Because

of their low cost, configuration flexibility, and compact program code, the 56F8345 and 56F8145 are

well-suited for many applications. The devices include many peripherals that are especially useful for

motion control, smart appliances, steppers, encoders, tachometers, limit switches, power supply and

control, automotive control (56F8345 only), engine management, noise suppression, remote utility

metering, industrial control for power, lighting, and automation applications.

The 56800E core is based on a Harvard-style architecture consisting of three execution units operating in

parallel, allowing as many as six operations per instruction cycle. The MCU-style programming model and

optimized instruction set allow straightforward generation of efficient, compact DSP and control code.

The instruction set is also highly efficient for C/C++ Compilers to enable rapid development of optimized

control applications.

The 56F8345 and 56F8145 support program execution from internal memories. Two data operands can be

accessed from the on-chip data RAM per instruction cycle. These devices also provide two external

dedicated interrupt lines and up to 49 General Purpose Input/Output (GPIO) lines, depending on peripheral

configuration.

56F8145 Features

The 56F8145 controller includes 128KB of Program Flash, programmable through the JTAG port, and

8KB of Data RAM. A total of 8KB of Boot Flash is incorporated for easy customer inclusion of

field-programmable software routines that can be used to program the main Program Flash memory area.

The Program Flash memory can be independently bulk erased or erased in pages; Program Flash page

erase size is 1KB. The Boot Flash page erase size is 512 bytes; Boot Flash memory can also be either bulk

or page erased.

A key application-specific feature of the 56F8145 is the inclusion of one Pulse Width Modulator (PWM)

module. This module incorporates three complementary, individually programmable PWM signal output

pairs and can also support six independent PWM functions to enhance motor control functionality.

Complementary operation permits programmable dead time insertion, distortion correction via current

sensing by software, and separate top and bottom output polarity control. The up-counter value is

programmable to support a continuously variable PWM frequency. Edge-aligned and center-aligned

synchronous pulse width control (0% to 100% modulation) is supported. The device is capable of

controlling most motor types: ACIM (AC Induction Motors); both BDC and BLDC (Brush and Brushless

DC motors); SRM and VRM (Switched and Variable Reluctance Motors); and stepper motors. The PWM

incorporates fault protection and cycle-by-cycle current limiting with sufficient output drive capability to

directly drive standard optoisolators. A “smoke-inhibit”, write-once protection feature for key parameters

is also included. A patented PWM waveform distortion correction circuit is also provided. The PWM is

double-buffered and includes interrupt controls to permit integral reload rates to be programmable from 1

to 16. The PWM module provides reference outputs to synchronize the Analog-to-Digital Converters

through two channels of Quad Timer C.

The 56F8145 incorporates a Quadrature Decoder capable of capturing all four transitions on the two-phase

inputs, permitting generation of a number proportional to actual position. Speed computation capabilities

accommodate both fast- and slow-moving shafts. An integrated watchdog timer in the Quadrature Decoder

can be programmed with a time-out value to alert when no shaft motion is detected. Each input is filtered

to ensure only true transitions are recorded.

This controller also provides a full set of standard programmable peripherals that include two Serial

Communications Interfaces (SCIs); two Serial Peripheral Interfaces (SPIs); and two Quad Timers. Any of

these interfaces can be used as General Purpose Input/Outputs (GPIOs) if that function is not required. An

internal interrupt controller is also a part of the 56F8145.

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HCS12X HCS12X Microcontroller IC 16-Bit 50MHz 128KB (128K x 8) FLASH 80-QFP (14x14)

Introduction

The MC9S12XE-Family of micro controllers is a further development of the S12XD-Family including

new features for enhanced system integrity and greater functionality. These new features include a

Memory Protection Unit (MPU) and Error Correction Code (ECC) on the Flash memory together with

enhanced EEPROM functionality (EEE), an enhanced XGATE, an Internally filtered, frequency

modulated Phase Locked Loop (IPLL) and an enhanced ATD. The E-Family extends the S12X product

range up to 1MB of Flash memory with increased I/O capability in the 208-pin version of the flagship

MC9S12XE100.

The MC9S12XE-Family delivers 32-bit performance with all the advantages and efficiencies of a 16 bit

MCU. It retains the low cost, power consumption, EMC and code-size efficiency advantages currently

enjoyed by users of Freescale’s existing 16-Bit MC9S12 and S12X MCU families. There is a high level of

compatibility between the S12XE and S12XD families.

The MC9S12XE-Family features an enhanced version of the performance-boosting XGATE co-processor

which is programmable in “C” language and runs at twice the bus frequency of the S12X with an

instruction set optimized for data movement, logic and bit manipulation instructions and which can service

any peripheral module on the device. The new enhanced version has improved interrupt handling

capability and is fully compatible with the existing XGATE module.

The MC9S12XE-Family is composed of standard on-chip peripherals including up to 64Kbytes of RAM,

eight asynchronous serial communications interfaces (SCI), three serial peripheral interfaces (SPI), an 8-

channel IC/OC enhanced capture timer (ECT), two 16-channel, 12-bit analog-to-digital converters, an 8-

channel pulse-width modulator (PWM), five CAN 2.0 A, B software compatible modules (MSCAN12),

two inter-IC bus blocks (IIC), an 8-channel 24-bit periodic interrupt timer (PIT) and an 8-channel 16-bit

standard timer module (TIM).

The MC9S12XE-Family uses 16-bit wide accesses without wait states for all peripherals and memories.

The non-multiplexed expanded bus interface available on the 144/208-Pin versions allows an easy

interface to external memories.

In addition to the I/O ports available in each module, up to 26 further I/O ports are available with interrupt

capability allowing Wake-Up from STOP or WAIT modes. The MC9S12XE-Family is available in 208-

Pin MAPBGA, 144-Pin LQFP, 112-Pin LQFP or 80-Pin QFP options.

Features

• 16-Bit CPU12X

— Upward compatible with MC9S12 instruction set with the exception of five Fuzzy instructions

(MEM, WAV, WAVR, REV, REVW) which have been removed

— Enhanced indexed addressing

— Access to large data segments independent of PPAGE

• INT (interrupt module)

— Eight levels of nested interrupts

— Flexible assignment of interrupt sources to each interrupt level.

— External non-maskable high priority interrupt (XIRQ)

— Internal non-maskable high priority Memory Protection Unit interrupt

— Up to 24 pins on ports J, H and P configurable as rising or falling edge sensitive interrupts

• EBI (external bus interface)(available in 208-Pin and 144-Pin packages only)

— Up to four chip select outputs to select 16K, 1M, 2M and up to 4MByte address spaces

— Each chip select output can be configured to complete transaction on either the time-out of one

of the two wait state generators or the deassertion of EWAIT signal

• MMC (module mapping control)

• DBG (debug module)

— Monitoring of CPU and/or XGATE busses with tag-type or force-type breakpoint requests

— 64 x 64-bit circular trace buffer captures change-of-flow or memory access information

• BDM (background debug mode)

• MPU (memory protection unit)

— 8 address regions definable per active program task

— Address range granularity as low as 8-bytes

— No write / No execute Protection Attributes

— Non-maskable interrupt on access violation

• XGATE

— Programmable, high performance I/O coprocessor module

— Transfers data to or from all peripherals and RAM without CPU intervention or CPU wait states

— Performs logical, shifts, arithmetic, and bit operations on data

— Can interrupt the HCS12X CPU signalling transfer completion

— Triggers from any hardware module as well as from the CPU possible

— Two interrupt levels to service high priority tasks

— Hardware support for stack pointer initialisation

• OSC_LCP (oscillator)

— Low power loop control Pierce oscillator utilizing a 4MHz to 16MHz crystal

— Good noise immunity

— Full-swing Pierce option utilizing a 2MHz to 40MHz crystal

— Transconductance sized for optimum start-up margin for typical crystals

• IPLL (Internally filtered, frequency modulated phase-locked-loop clock generation)

— No external components required

— Configurable option to spread spectrum for reduced EMC radiation (frequency modulation)

• CRG (clock and reset generation)

— COP watchdog

— Real time interrupt

— Clock monitor

— Fast wake up from STOP in self clock mode

• Memory Options

— 128K, 256k, 384K, 512K, 768K and 1M byte Flash

— 2K, 4K byte emulated EEPROM

— 12K, 16K, 24K, 32K, 48K and 64K Byte RAM

• Flash General Features

— 64 data bits plus 8 syndrome ECC (Error Correction Code) bits allow single bit failure

correction and double fault detection

— Erase sector size 1024 bytes

— Automated program and erase algorithm

• D-Flash Features

— Up to 32 Kbytes of D-Flash memory with 256 byte sectors for user access.

— Dedicated commands to control access to the D-Flash memory over EEE operation.

— Single bit fault correction and double bit fault detection within a word during read operations.

— Automated program and erase algorithm with verify and generation of ECC parity bits.

— Fast sector erase and word program operation.

— Ability to program up to four words in a burst sequence

• Emulated EEPROM Features

— Automatic EEE file handling using an internal Memory Controller.

— Automatic transfer of valid EEE data from D-Flash memory to buffer RAM on reset.

— Ability to monitor the number of outstanding EEE related buffer RAM words left to be

programmed into D-Flash memory.

— Ability to disable EEE operation and allow priority access to the D-Flash memory.

— Ability to cancel all pending EEE operations and allow priority access to the D-Flash memory.

• Two 16-channel, 12-bit Analog-to-Digital Converters

— 8/10/12 Bit resolution

— 3µs, 10-bit single conversion time

— Left/right, signed/unsigned result data

— External and internal conversion trigger capability

— Internal oscillator for conversion in Stop modes

— Wake from low power modes on analog comparison > or <= match

• Five MSCAN (1 M bit per second, CAN 2.0 A, B software compatible modules)

— Five receive and three transmit buffers

— Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit, or 8 x 8 bit

— Four separate interrupt channels for Rx, Tx, error, and wake-up

— Low-pass filter wake-up function

— Loop-back for self-test operation

• ECT (enhanced capture timer)

— 8 x 16-bit channels for input capture or output compare

— 16-bit free-running counter with 8-bit precision prescaler

— 16-bit modulus down counter with 8-bit precision prescaler

— Four 8-bit or two 16-bit pulse accumulators

• TIM (standard timer module)

— 8 x 16-bit channels for input capture or output compare

— 16-bit free-running counter with 8-bit precision prescaler

— 1 x 16-bit pulse accumulator

• PIT (periodic interrupt timer)

— Up to eight timers with independent time-out periods

— Time-out periods selectable between 1 and 224 bus clock cycles

— Time-out interrupt and peripheral triggers

• 8 PWM (pulse-width modulator) channels

— 8 channel x 8-bit or 4 channel x 16-bit Pulse Width Modulator

— programmable period and duty cycle per channel

— Center- or left-aligned outputs

— Programmable clock select logic with a wide range of frequencies

— Fast emergency shutdown input

• Three Serial Peripheral Interface Modules (SPI)

— Configurable for 8 or 16-bit data size

• Eight Serial Communication Interfaces (SCI)

— Standard mark/space non-return-to-zero (NRZ) format

— Selectable IrDA 1.4 return-to-zero-inverted (RZI) format with programmable pulse widths

• Two Inter-IC bus (IIC) Modules

— Multi-master operation

— Software programmable for one of 256 different serial clock frequencies

— Broadcast mode support

— 10-bit address support

• On-Chip Voltage Regulator

— Two parallel, linear voltage regulators with bandgap reference

— Low-voltage detect (LVD) with low-voltage interrupt (LVI)

— Power-on reset (POR) circuit

— 3.3V and 5V range operation

— Low-voltage reset (LVR)

• Low-power wake-up timer (API)

— Available in all modes including Full Stop Mode

— Trimmable to +-5% accuracy

— Time-out periods range from 0.2ms to ~13s with a 0.2ms resolution

• Input/Output

— Up to 152 general-purpose input/output (I/O) pins plus 2 input-only pins

— Hysteresis and configurable pull up/pull down device on all input pins

— Configurable drive strength on all output pins

• Package Options

— 208-pin MAPBGA

— 144-pin low-profile quad flat-pack (LQFP)

— 112-pin low-profile quad flat-pack (LQFP)

— 80-pin quad flat-pack (QFP)

• 50MHz maximum CPU bus frequency, 100MHz maximum XGATE bus frequency

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