NXP USA Inc.

HCS12X HCS12X Microcontroller IC 16-Bit 80MHz 512KB (512K x 8) FLASH 80-QFP (14x14)

MC9S12XDP512

Covers

S12XD, S12XB & S12XA Families

Introduction

The MC9S12XD family will retain the low cost, power consumption, EMC and code-size efficiency

advantages currently enjoyed by users of Freescale's existing 16-Bit MC9S12 MCU Family.

Based around an enhanced S12 core, the MC9S12XD family will deliver 2 to 5 times the performance of

a 25-MHz S12 whilst retaining a high degree of pin and code compatibility with the S12.

The MC9S12XD family introduces the performance boosting XGATE module. Using enhanced DMA

functionality, this parallel processing module offloads the CPU by providing high-speed data processing

and transfer between peripheral modules, RAM, Flash EEPROM and I/O ports. Providing up to 80 MIPS

of performance additional to the CPU, the XGATE can access all peripherals, Flash EEPROM and the

RAM block.

The MC9S12XD family is composed of standard on-chip peripherals including up to 512 Kbytes of Flash

EEPROM, 32 Kbytes of RAM, 4 Kbytes of EEPROM, six asynchronous serial communications interfaces

(SCI), three serial peripheral interfaces (SPI), an 8-channel IC/OC enhanced capture timer, an 8-channel,

10-bit analog-to-digital converter, a 16-channel, 10-bit analog-to-digital converter, an 8-channel

pulse-width modulator (PWM), five CAN 2.0 A, B software compatible modules (MSCAN12), two

inter-IC bus blocks, and a periodic interrupt timer. The MC9S12XD family has full 16-bit data paths

throughout.

The non-multiplexed expanded bus interface available on the 144-pin versions allows an easy interface to

external memories

The inclusion of a PLL circuit allows power consumption and performance to be adjusted to suit

operational requirements. System power consumption can be further improved with the new “fast exit from

stop mode” feature.

In addition to the I/O ports available in each module, up to 25 further I/O ports are available with interrupt

capability allowing wake-up from stop or wait mode.

Family members in 144-pin LQFP will be available with external bus interface and parts in 112-pin LQFP

or 80-pin QFP package without external bus interface. See Appendix E Derivative Differencesfor package

options.

MC9S12XD/B/A Family Features

• HCS12X Core

— 16-bit HCS12X CPU

– Upward compatible with MC9S12 instruction set

– Interrupt stacking and programmer’s model identical to MC9S12

– Instruction queue

– Enhanced indexed addressing

– Enhanced instruction set

— EBI (external bus interface)

— MMC (module mapping control)

— INT (interrupt controller)

— DBG (debug module to monitor HCS12X CPU and XGATE bus activity)

— BDM (background debug mode)

• XGATE (peripheral coprocessor)

— Parallel processing module off loads the CPU by providing high-speed data processing and

transfer

— Data transfer between Flash EEPROM, RAM, peripheral modules, and I/O ports

• PIT (periodic interrupt timer)

— Four timers with independent time-out periods

— Time-out periods selectable between 1 and 224 bus clock cycles

• CRG (clock and reset generator)

— Low noise/low power Pierce oscillator

— PLL

— COP watchdog

— Real time interrupt

— Clock monitor

— Fast wake-up from stop mode

• Port H & Port J with interrupt functionality

— Digital filtering

— Programmable rising or falling edge trigger

• Memory

— 512, 256 and 128-Kbyte Flash EEPROM

— 4 and 2-Kbyte EEPROM

— 32, 16 and 12-Kbyte RAM

• One 16-channel and one 8-channel ADC (analog-to-digital converter)

— 10-bit resolution

— External and internal conversion trigger capabilityFiveFourTwo 1M bit per second,

CAN 2.0 A, B software compatible modules

— Five receive and three transmit buffers

— Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit, or 8 x 8 bit

— Four separate interrupt channels for Rx, Tx, error, and wake-up

— Low-pass filter wake-up function

— Loop-back for self-test operation

• ECT (enhanced capture timer)

— 16-bit main counter with 7-bit prescaler

— 8 programmable input capture or output compare channels

— Four 8-bit or two 16-bit pulse accumulators

• 8 PWM (pulse-width modulator) channels

— Programmable period and duty cycle

— 8-bit 8-channel or 16-bit 4-channel

— Separate control for each pulse width and duty cycle

— Center-aligned or left-aligned outputs

— Programmable clock select logic with a wide range of frequencies

— Fast emergency shutdown input

• Serial interfaces

— SixFourTwo asynchronous serial communication interfaces (SCI) with additional LIN support

and selectable IrDA 1.4 return-to-zero-inverted (RZI) format with programmable pulse width

— ThreeTwo Synchronous Serial Peripheral Interfaces (SPI)

• TwoOne IIC (Inter-IC bus) Modules

— Compatible with IIC bus standard

— Multi-master operation

— Software programmable for one of 256 different serial clock frequencies

• On-Chip Voltage Regulator

— Two parallel, linear voltage regulators with bandgap reference

— Low-voltage detect (LVD) with low-voltage interrupt (LVI)

— Power-on reset (POR) circuit

— 3.3-V–5.5-V operation

— Low-voltage reset (LVR)

— Ultra low-power wake-up timer

• 144-pin LQFP, 112-pin LQFP, and 80-pin QFP packages

— I/O lines with 5-V input and drive capability

— Input threshold on external bus interface inputs switchable for 3.3-V or 5-V operation

— 5-V A/D converter inputs

— Operation at 80 MHz equivalent to 40-MHz bus speed

• Development support

— Single-wire background debug™ mode (BDM)

— Four on-chip hardware breakpoints

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S12Z S12 MagniV Microcontroller IC 16-Bit 32MHz 32KB (32K x 8) FLASH 48-LQFP (7x7)

Introduction

The MC9S12ZVM-Family is an automotive 16-bit microcontroller family using the NVM + UHV

technology that offers the capability to integrate 40 V analog components. This family reuses many

features from the existing S12/S12X portfolio. The particular differentiating features of this family are the

enhanced S12Z core, the combination of dual-ADC synchronized with PWM generation and the

integration of “high-voltage” analog modules, including the voltage regulator (VREG), Gate Drive Unit

(GDU) and a Local Interconnect Network (LIN) physical layer. These features enable a fully integrated

single chip solution to drive up to 6 external power MOSFETs for BLDC or PMSM motor drive

applications.

The MC9S12ZVM-Family includes error correction code (ECC) on RAM and flash memory, EEPROM

for diagnostic or data storage, a fast analog-to-digital converter (ADC) and a frequency modulated phase

locked loop (IPLL) that improves the EMC performance. The MC9S12ZVM-Family delivers an

optimized solution with the integration of several key system components into a single device, optimizing

system architecture and achieving significant space savings. The MC9S12ZVM-Family delivers all the

advantages and efficiencies of a 16-bit MCU while retaining the low cost, power consumption, EMC, and

code-size efficiency advantages currently enjoyed by users of existing S12(X) families. The

MC9S12ZVM-Family is available in different pin-out options, using the 64-pin LQFP-EP and 48-pin

LQFP-EP packages to accommodate LIN, CAN and external PWM based application interfaces. In

addition to the I/O ports available in each module, further I/O ports are available with interrupt capability

allowing wake-up from stop or wait modes.

The MC9S12ZVM-Family is a general-purpose family of devices suitable for a range of applications,

including:

• 3-phase sensorless BLDC motor control for

— Fuel pump

— Water pump

— Oil pump

— A/C compressor

— HVAC blower

— Engine cooling fan

— Electric vehicle battery cooling fan

• Brush DC motor control requiring driving in 2 directions, along with PWM control for

— Reversible wiper

— Trunk opener

Chip-Level Features

On-chip modules available within the family include the following features:

• S12Z CPU core

• 128, 64, 32 or 16KB on-chip flash with ECC

• 512 or128 byte EEPROM with ECC

• 8, 4 or 2 KB on-chip SRAM with ECC

• Phase locked loop (IPLL) frequency multiplier with internal filter

• 1 MHz internal RC oscillator with +/-1.3% accuracy over rated temperature range

• 4-20MHz amplitude controlled pierce oscillator

• Internal COP (watchdog) module

• 6-channel, 15-bit pulse width modulator with fault protection (PMF) 

• Low side and high side FET pre-drivers for each phase

— Gate drive pre-regulator

— LDO (Low Dropout Voltage Regulator) (typically 11V)

— High side gate supply generated using bootstrap circuit with external diode and capacitor

— Sustaining charge pump with two external capacitors and diodes

— High side drain (HD) monitoring on internal ADC channel using HD/5 voltage

• Two parallel analog-to-digital converters (ADC) with 12-bit resolution and up to 9 channels

available on external pins

• Programmable Trigger Unit (PTU) for synchronization of PMF and ADC

• One serial peripheral interface (SPI) module

• One serial communication interface (SCI) module with interface to internal LIN physical layer

transceiver (with RX connected to a timer channel for frequency calibration purposes, if desired)

• Up to one additional SCI (not connected to LIN physical layer)

• On-chip LIN physical layer transceiver fully compliant with the LIN 2.2 standard

(S12ZVML versions)

• One High Voltage physical interface. (S12ZVM32, S12ZVM16 versions only)

• 4-channel timer module (TIM) with input capture/output compare

• MSCAN (1 Mbit/s, CAN 2.0 A, B software compatible) module

• On-chip voltage regulator (VREG) for regulation of input supply and all internal voltages

— Optional VREG ballast control output to supply an external CAN physical layer

• Two current sense circuits for overcurrent detection or torque measurement

• Autonomous periodic interrupt (API)

• 20mA high-current output for use as Hall sensor supply

• Supply voltage sense with low battery warning

• Chip temperature sensor

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HCS12 HCS12 Microcontroller IC 16-Bit 25MHz 96KB (96K x 8) FLASH 48-LQFP (7x7)

Introduction

The MC9S12C-Family / MC9S12GC-Family are 48/52/80 pin Flash-based MCU families, which deliver

the power and flexibility of the 16-bit core to a whole new range of cost and space sensitive, general

purpose industrial and automotive network applications. All MC9S12C-Family / MC9S12GC-Family

members feature standard on-chip peripherals including a 16-bit central processing unit (CPU12), up to

128K bytes of Flash EEPROM, up to 4K bytes of RAM, an asynchronous serial communications interface

(SCI), a serial peripheral interface (SPI), an 8-channel 16-bit timer module (TIM), a 6-channel 8-bit pulse

width modulator (PWM), an 8-channel, 10-bit analog-to-digital converter (ADC).

The MC9S12C128-Family members also feature a CAN 2.0 A, B software compatible module

(MSCAN12).

All MC9S12C-Family / MC9S12GC-Family devices feature full 16-bit data paths throughout. The

inclusion of a PLL circuit allows power consumption and performance to be adjusted to suit operational

requirements. In addition to the I/O ports available in each module, up to 10 dedicated I/O port bits are

available with wake-up capability from stop or wait mode. The devices are available in 48-, 52-, and 80-

pin QFP packages, with the 80-pin version pin compatible to the HCS12 A, B, and D Family derivatives

Features

• 16-bit HCS12 core:

— HCS12 CPU

– Upward compatible with M68HC11 instruction set

– Interrupt stacking and programmer’s model identical to M68HC11

– Instruction queue

– Enhanced indexed addressing

— MMC (memory map and interface)

— INT (interrupt control)

— BDM (background debug mode)

— DBG12 (enhanced debug12 module, including breakpoints and change-of-flow trace buffer)

— MEBI (multiplexed expansion bus interface) available only in 80-pin package version

• Wake-up interrupt inputs:

— Up to 12 port bits available for wake up interrupt function with digital filtering

• Memory options:

— 16K or 32Kbyte Flash EEPROM (erasable in 512-byte sectors)

64K, 96K, or 128Kbyte Flash EEPROM (erasable in 1024-byte sectors)

— 1K, 2K or 4K Byte RAM

• Analog-to-digital converters:

— One 8-channel module with 10-bit resolution

— External conversion trigger capability

• Available on MC9S12C Family:

— One 1M bit per second, CAN 2.0 A, B software compatible module

— Five receive and three transmit buffers

— Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit, or 8 x 8 bit

— Four separate interrupt channels for Rx, Tx, error, and wake-up

— Low-pass filter wake-up function

— Loop-back for self test operation

• Timer module (TIM):

— 8-channel timer

— Each channel configurable as either input capture or output compare

— Simple PWM mode

— Modulo reset of timer counter

— 16-bit pulse accumulator

— External event counting

— Gated time accumulation

• PWM module:

— Programmable period and duty cycle

— 8-bit 6-channel or 16-bit 3-channel

— Separate control for each pulse width and duty cycle

— Center-aligned or left-aligned outputs

— Programmable clock select logic with a wide range of frequencies

— Fast emergency shutdown input

• Serial interfaces:

— One asynchronous serial communications interface (SCI)

— One synchronous serial peripheral interface (SPI)

• CRG (clock reset generator module)

— Windowed COP watchdog

— Real time interrupt

— Clock monitor

— Pierce or low current Colpitts oscillator

— Phase-locked loop clock frequency multiplier

— Limp home mode in absence of external clock

— Low power 0.5MHz to 16MHz crystal oscillator reference clock

• Operating frequency:

— 32MHz equivalent to 16MHz bus speed for single chip

— 32MHz equivalent to 16MHz bus speed in expanded bus modes

— Option of 9S12C Family: 50MHz equivalent to 25MHz bus speed

— All 9S12GC Family members allow a 50MHz operating frequency.

• Internal 2.5V regulator:

— Supports an input voltage range from 2.97V to 5.5V

— Low power mode capability

— Includes low voltage reset (LVR) circuitry

— Includes low voltage interrupt (LVI) circuitry

• 48-pin LQFP, 52-pin LQFP, or 80-pin QFP package:

— Up to 58 I/O lines with 5V input and drive capability (80-pin package)

— Up to 2 dedicated 5V input only lines (IRQ, XIRQ)

— 5V 8 A/D converter inputs and 5V I/O

• Development support:

— Single-wire background debug™ mode (BDM)

— On-chip hardware breakpoints

— Enhanced DBG12 debug features

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