NXP USA Inc.

HCS12X HCS12X Microcontroller IC 16-Bit 50MHz 1MB (1M x 8) FLASH 144-LQFP (20x20)

MC9S12XEP100

Covers MC9S12XE Family

Introduction

The MC9S12XE-Family of micro controllers is a further development of the S12XD-Family including

new features for enhanced system integrity and greater functionality. These new features include a

Memory Protection Unit (MPU) and Error Correction Code (ECC) on the Flash memory together with

enhanced EEPROM functionality (EEE), an enhanced XGATE, an Internally filtered, frequency

modulated Phase Locked Loop (IPLL) and an enhanced ATD. The E-Family extends the S12X product

range up to 1MB of Flash memory with increased I/O capability in the 208-pin version of the flagship

MC9S12XE100.

The MC9S12XE-Family delivers 32-bit performance with all the advantages and efficiencies of a 16 bit

MCU. It retains the low cost, power consumption, EMC and code-size efficiency advantages currently

enjoyed by users of Freescale’s existing 16-Bit MC9S12 and S12X MCU families. There is a high level of

compatibility between the S12XE and S12XD families.

The MC9S12XE-Family features an enhanced version of the performance-boosting XGATE co-processor

which is programmable in “C” language and runs at twice the bus frequency of the S12X with an

instruction set optimized for data movement, logic and bit manipulation instructions and which can service

any peripheral module on the device. The new enhanced version has improved interrupt handling

capability and is fully compatible with the existing XGATE module.

The MC9S12XE-Family is composed of standard on-chip peripherals including up to 64Kbytes of RAM,

eight asynchronous serial communications interfaces (SCI), three serial peripheral interfaces (SPI), an 8-

channel IC/OC enhanced capture timer (ECT), two 16-channel, 12-bit analog-to-digital converters, an 8-

channel pulse-width modulator (PWM), five CAN 2.0 A, B software compatible modules (MSCAN12),

two inter-IC bus blocks (IIC), an 8-channel 24-bit periodic interrupt timer (PIT) and an 8-channel 16-bit

standard timer module (TIM).

The MC9S12XE-Family uses 16-bit wide accesses without wait states for all peripherals and memories.

The non-multiplexed expanded bus interface available on the 144/208-Pin versions allows an easy

interface to external memories.

In addition to the I/O ports available in each module, up to 26 further I/O ports are available with interrupt

capability allowing Wake-Up from STOP or WAIT modes. The MC9S12XE-Family is available in 208-

Pin MAPBGA, 144-Pin LQFP, 112-Pin LQFP or 80-Pin QFP options.

Features

• 16-Bit CPU12X

— Upward compatible with MC9S12 instruction set with the exception of five Fuzzy instructions

(MEM, WAV, WAVR, REV, REVW) which have been removed

— Enhanced indexed addressing

— Access to large data segments independent of PPAGE

• INT (interrupt module)

— Eight levels of nested interrupts

— Flexible assignment of interrupt sources to each interrupt level.

— External non-maskable high priority interrupt (XIRQ)

— Internal non-maskable high priority Memory Protection Unit interrupt

— Up to 24 pins on ports J, H and P configurable as rising or falling edge sensitive interrupts

• EBI (external bus interface)(available in 208-Pin and 144-Pin packages only)

— Up to four chip select outputs to select 16K, 1M, 2M and up to 4MByte address spaces

— Each chip select output can be configured to complete transaction on either the time-out of one

of the two wait state generators or the deassertion of EWAIT signal

• MMC (module mapping control)

• DBG (debug module)

— Monitoring of CPU and/or XGATE busses with tag-type or force-type breakpoint requests

— 64 x 64-bit circular trace buffer captures change-of-flow or memory access information

• BDM (background debug mode)

• MPU (memory protection unit)

— 8 address regions definable per active program task

— Address range granularity as low as 8-bytes

— No write / No execute Protection Attributes

— Non-maskable interrupt on access violation

• XGATE

— Programmable, high performance I/O coprocessor module

— Transfers data to or from all peripherals and RAM without CPU intervention or CPU wait states

— Performs logical, shifts, arithmetic, and bit operations on data

— Can interrupt the HCS12X CPU signalling transfer completion

— Triggers from any hardware module as well as from the CPU possible

— Two interrupt levels to service high priority tasks

— Hardware support for stack pointer initialisation

• OSC_LCP (oscillator)

— Low power loop control Pierce oscillator utilizing a 4MHz to 16MHz crystal

— Good noise immunity

— Full-swing Pierce option utilizing a 2MHz to 40MHz crystal

— Transconductance sized for optimum start-up margin for typical crystals

• IPLL (Internally filtered, frequency modulated phase-locked-loop clock generation)

— No external components required

— Configurable option to spread spectrum for reduced EMC radiation (frequency modulation)

• CRG (clock and reset generation)

— COP watchdog

— Real time interrupt

— Clock monitor

— Fast wake up from STOP in self clock mode

• Memory Options

— 128K, 256k, 384K, 512K, 768K and 1M byte Flash

— 2K, 4K byte emulated EEPROM

— 12K, 16K, 24K, 32K, 48K and 64K Byte RAM

• Flash General Features

— 64 data bits plus 8 syndrome ECC (Error Correction Code) bits allow single bit failure

correction and double fault detection

— Erase sector size 1024 bytes

— Automated program and erase algorithm

• D-Flash Features

— Up to 32 Kbytes of D-Flash memory with 256 byte sectors for user access.

— Dedicated commands to control access to the D-Flash memory over EEE operation.

— Single bit fault correction and double bit fault detection within a word during read operations.

— Automated program and erase algorithm with verify and generation of ECC parity bits.

— Fast sector erase and word program operation.

— Ability to program up to four words in a burst sequence

• Emulated EEPROM Features

— Automatic EEE file handling using an internal Memory Controller.

— Automatic transfer of valid EEE data from D-Flash memory to buffer RAM on reset.

— Ability to monitor the number of outstanding EEE related buffer RAM words left to be

programmed into D-Flash memory.

— Ability to disable EEE operation and allow priority access to the D-Flash memory.

— Ability to cancel all pending EEE operations and allow priority access to the D-Flash memory.

• Two 16-channel, 12-bit Analog-to-Digital Converters

— 8/10/12 Bit resolution

— 3µs, 10-bit single conversion time

— Left/right, signed/unsigned result data

— External and internal conversion trigger capability

— Internal oscillator for conversion in Stop modes

— Wake from low power modes on analog comparison > or <= match

• Five MSCAN (1 M bit per second, CAN 2.0 A, B software compatible modules)

— Five receive and three transmit buffers

— Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit, or 8 x 8 bit

— Four separate interrupt channels for Rx, Tx, error, and wake-up

— Low-pass filter wake-up function

— Loop-back for self-test operation

• ECT (enhanced capture timer)

— 8 x 16-bit channels for input capture or output compare

— 16-bit free-running counter with 8-bit precision prescaler

— 16-bit modulus down counter with 8-bit precision prescaler

— Four 8-bit or two 16-bit pulse accumulators

• TIM (standard timer module)

— 8 x 16-bit channels for input capture or output compare

— 16-bit free-running counter with 8-bit precision prescaler

— 1 x 16-bit pulse accumulator

• PIT (periodic interrupt timer)

— Up to eight timers with independent time-out periods

— Time-out periods selectable between 1 and 224 bus clock cycles

— Time-out interrupt and peripheral triggers

• 8 PWM (pulse-width modulator) channels

— 8 channel x 8-bit or 4 channel x 16-bit Pulse Width Modulator

— programmable period and duty cycle per channel

— Center- or left-aligned outputs

— Programmable clock select logic with a wide range of frequencies

— Fast emergency shutdown input

• Three Serial Peripheral Interface Modules (SPI)

— Configurable for 8 or 16-bit data size

• Eight Serial Communication Interfaces (SCI)

— Standard mark/space non-return-to-zero (NRZ) format

— Selectable IrDA 1.4 return-to-zero-inverted (RZI) format with programmable pulse widths

• Two Inter-IC bus (IIC) Modules

— Multi-master operation

— Software programmable for one of 256 different serial clock frequencies

— Broadcast mode support

— 10-bit address support

• On-Chip Voltage Regulator

— Two parallel, linear voltage regulators with bandgap reference

— Low-voltage detect (LVD) with low-voltage interrupt (LVI)

— Power-on reset (POR) circuit

— 3.3V and 5V range operation

— Low-voltage reset (LVR)

• Low-power wake-up timer (API)

— Available in all modes including Full Stop Mode

— Trimmable to +-5% accuracy

— Time-out periods range from 0.2ms to ~13s with a 0.2ms resolution

• Input/Output

— Up to 152 general-purpose input/output (I/O) pins plus 2 input-only pins

— Hysteresis and configurable pull up/pull down device on all input pins

— Configurable drive strength on all output pins

• Package Options

— 208-pin MAPBGA

— 144-pin low-profile quad flat-pack (LQFP)

— 112-pin low-profile quad flat-pack (LQFP)

— 80-pin quad flat-pack (QFP)

• 50MHz maximum CPU bus frequency, 100MHz maximum XGATE bus frequency

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56800E 56F8xxx Microcontroller IC 16-Bit 32MHz 16KB (8K x 16) FLASH 48-LQFP (7x7)

MC56F8006/MC56F8002 Digital Signal Controller

This document applies to parts marked with 2M53M.

The 56F8006/56F8002 is a member of the 56800E core-based family of digital signal controllers (DSCs). It combines, on a

single chip, the processing power of a DSP and the functionality of a microcontroller with a flexible set of

peripherals to create a cost-effective solution. Because of its low cost, configuration flexibility, and compact program

code, the 56F8006/56F8002 is well-suited for many applications. It includes many peripherals that are especially

useful for cost-sensitive applications, including:

• Industrial control

• Home appliances

• Smart sensors

• Fire and security systems

• Switched-mode power supply and power management

• Power metering

• Motor control (ACIM, BLDC, PMSM, SR, and stepper)

• Handheld power tools

• Arc detection

• Medical device/equipment

• Instrumentation

• Lighting ballast

The 56800E core is based on a dual Harvard-style architecture consisting of three execution units operating in parallel, allowing

as many as six operations per instruction cycle. The MCU-style programming model and optimized instruction set allow

straightforward generation of efficient, compact DSP and control code. The instruction set is also highly efficient for C compilers

to enable rapid development of optimized control applications.

The 56F8006/56F8002 supports program execution from internal memories. Two data operands can be accessed from the on-chip

data RAM per instruction cycle. The 56F8006/56F8002 also offers up to 40 general-purpose input/output (GPIO) lines,

depending on peripheral configuration.

The 56F8006/56F8002 digital signal controller includes up to 16 KB of program flash and 2 KB of unified data/program 

RAM. Program flash memory can be independently bulk erased or erased in small pages of 512 bytes (256 words).

On-chip features include:

• Up to 32 MIPS at 32 MHz core frequency

• DSP and MCU functionality in a unified, C-efficient architecture

• On-chip memory

– 56F8006: 16 KB (8K x 16) flash memory

– 56F8002: 12 KB (6K x 16) flash memory

– 2 KB (1K x 16) unified data/program RAM

• One 6-channel PWM module

• Two 28-channel, 12-bit analog-to-digital converters (ADCs)

• Two programmable gain amplifiers (PGA) with gain up to 32x

• Three analog comparators

• One programmable interval timer (PIT)

• One high-speed serial communication interface (SCI) with

LIN slave functionality

• One serial peripheral interface (SPI)

• One 16-bit dual timer (2 x 16 bit timers)

• One programmable delay block (PDB)

• One SMBus compatible inter-integrated circuit (I2C) port

• One real time counter (RTC)

• Computer operating properly (COP)/watchdog

• Two on-chip relaxation oscillators — 1 kHz and 8 MHz (400 kHz at standby mode)

• Crystal oscillator

• Integrated power-on reset (POR) and low-voltage interrupt (LVI) module

• JTAG/enhanced on-chip emulation (OnCE™) for unobtrusive, real-time debugging

• Up to 40 GPIO lines

• 28-pin SOIC, 32-pin LQFP, 32-pin PSDIP, and 48-pin LQFP packages 

56F8006/56F8002 Features

1 Core

• Efficient 16-bit 56800E family digital signal controller (DSC) engine with dual Harvard architecture

• As many as 32 million instructions per second (MIPS) at 32 MHz core frequency

• 155 basic instructions in conjunction with up to 20 address modes

• Single-cycle 16  16-bit parallel multiplier-accumulator (MAC)

• Four 36-bit accumulators, including extension bits

• 32-bit arithmetic and logic multi-bit shifter

• Parallel instruction set with unique DSP addressing modes

• Hardware DO and REP loops

• Three internal address buses

• Four internal data buses

• Instruction set supports DSP and controller functions

• Controller-style addressing modes and instructions for compact code

• Efficient C compiler and local variable support

• Software subroutine and interrupt stack with depth limited only by memory

• JTAG/enhanced on-chip emulation (EOnCE) for unobtrusive, processor speed–independent, real-time debugging

2 Operation Range

• 1.8 V to 3.6 V operation (power supplies and I/O)

• From power-on-reset: approximately 1.9 V to 3.6 V

• Ambient temperature operating range:

— –40 °C to 125 °C

3 Memory

• Dual Harvard architecture permits as many as three simultaneous accesses to program and data memory

• Flash security and protection that prevent unauthorized users from gaining access to the internal flash

• On-chip memory

— 16 KB of program flash for 56F8006 and 12 KB of program flash for 56F8002

— 2 KB of unified data/program RAM

• EEPROM emulation capability using flash

4 Interrupt Controller

• Five interrupt priority levels

— Three user programmable priority levels for each interrupt source: Level 0, 1, 2

— Unmaskable level 3 interrupts include: illegal instruction, hardware stack overflow, misaligned data access, SWI3

instruction. Maskable level 3 interrupts include: EOnCE step counter, EOnCE breakpoint unit, EOnCE trace

buffer

— Lowest-priority software interrupt: level LP

• Allow nested interrupt that higher priority level interrupt request can interrupt lower priority interrupt subroutine

• The masking of interrupt priority level is managed by the 56800E core

• One programmable fast interrupt that can be assigned to any interrupt source

• Notification to system integration module (SIM) to restart clock out of wait and stop states

• Ability to relocate interrupt vector table

5 Peripheral Highlights

• One multi-function, six-output pulse width modulator (PWM) module

— Up to 96 MHz PWM operating clock

— 15 bits of resolution

— Center-aligned and edge-aligned PWM signal mode

— Phase shifting PWM pulse generation

— Four programmable fault inputs with programmable digital filter

— Double-buffered PWM registers

— Separate deadtime insertions for rising and falling edges

— Separate top and bottom pulse-width correction by means of software

— Asymmetric PWM output within both Center Aligned and Edge Aligned operation

— Separate top and bottom polarity control

— Each complementary PWM signal pair allows selection of a PWM supply source from:

– PWM generator

– Internal timers

– Analog comparator outputs

• Two independent 12-bit analog-to-digital converters (ADCs)

— 2 x 14 channel external inputs plus seven internal inputs

— Support simultaneous and software triggering conversions

— ADC conversions can be synchronized by PWM and PDB modules

— Sampling rate up to 400 KSPS for 10- or 12-bit conversion result; 470 KSPS for 8-bit conversion result

— Two 16-word result registers

• Two programmable gain amplifier (PGAs)

— Each PGA is designed to amplify and convert differential signals to a single-ended value fed to one of the ADC

inputs

— 1X, 2X, 4X, 8X, 16X, or 32X gain

— Software and hardware triggers are available

— Integrated sample/hold circuit

— Includes additional calibration features:

– Offset calibration eliminates any errors in the internal reference used to generate the VDDA/2 output center

point

– Gain calibration can be used to verify the gain of the overall datapath

– Both features require software correction of the ADC result

• Three analog comparators (CMPs)

— Selectable input source includes external pins, internal DACs

— Programmable output polarity

— Output can drive timer input, PWM fault input, PWM source, external pin output, and trigger ADCs

— Output falling and rising edge detection able to generate interrupts

• One dual channel 16-bit multi-purpose timer module (TMR)

— Two independent 16-bit counter/timers with cascading capability

— Up to 96 MHz operating clock

— Each timer has capture and compare and quadrature decoder capability

— Up to 12 operating modes

— Four external inputs and two external outputs

• One serial communication interface (SCI) with LIN slave functionality

— Up to 96 MHz operating clock

— Full-duplex or single-wire operation

— Programmable 8- or 9- bit data format

— Two receiver wakeup methods:

– Idle line

– Address mark

— 1/16 bit-time noise detection

• One serial peripheral interface (SPI)

— Full-duplex operation

— Master and slave modes

— Programmable length transactions (2 to 16 bits)

— Programmable transmit and receive shift order (MSB as first or last bit transmitted)

— Maximum slave module frequency = module clock frequency/2

• One inter-integrated Circuit (I2C) port

— Operates up to 400 kbps

— Supports master and slave operation

— Supports 10-bit address mode and broadcasting mode

— Supports SMBus, Version 2

• One 16-bit programmable interval timer (PIT)

— 16 bit counter with programmable counter modulo

— Interrupt capability

• One 16-bit programmable delay block (PDB)

— 16 bit counter with programmable counter modulo and delay time

— Counter is initiated by positive transition of internal or external trigger pulse

— Supports two independently controlled delay pulses used to synchronize PGA and ADC conversions with input

trigger event

— Two PDB outputs can be ORed together to schedule two conversions from one input trigger event

— PDB outputs can be can be used to schedule precise edge placement for a pulsed output that generates the control

signal for the CMP windowing comparison

— Supports continuous or single shot mode

— Bypass mode supported

• Computer operating properly (COP)/watchdog timer capable of selecting different clock sources

— Programmable prescaler and timeout period

— Programmable wait, stop, and partial powerdown mode operation

— Causes loss of reference reset 128 cycles after loss of reference clock to the PLL is detected

— Choice of clock sources from four sources in support of EN60730 and IEC61508:

– On-chip relaxation oscillator

– External crystal oscillator/external clock source

– System clock (IPBus up to 32 MHz)

– On-chip low power 1 kHz oscillator

• Real-timer counter (RTC)

— 8-bit up-counter

— Three software selectable clock sources

– External crystal oscillator/external clock source

– On-chip low-power 1 kHz oscillator

– System bus (IPBus up to 32 MHz)

— Can signal the device to exit power down mode

• Phase lock loop (PLL) provides a high-speed clock to the core and peripherals

— Provides 3x system clock to PWM and dual timer and SCI

— Loss of lock interrupt

— Loss of reference clock interrupt

• Clock sources

— On-chip relaxation oscillator with two user selectable frequencies: 400 kHz for low speed mode, 8 MHz for

normal operation

— On-chip low-power 1 kHz oscillator can be selected as clock source to the RTC and/or COP

— External clock: crystal oscillator, ceramic resonator, and external clock source

• Power management controller (PMC)

— On-chip regulator for digital and analog circuitry to lower cost and reduce noise

— Integrated power-on reset (POR)

— Low-voltage interrupt with a user selectable trip voltage of 1.81 V or 2.31 V

— User selectable brown-out reset

— Run, wait, and stop modes

— Low-power run, wait, and stop modes

— Partial power down mode

• Up to 40 general-purpose I/O (GPIO) pins

— Individual control for each pin to be in peripheral or GPIO mode

— Individual input/output direction control for each pin in GPIO mode

— Hysteresis and configurable pullup device on all input pins

— Configurable slew rate and drive strength and optional input low pass filters on all output pins

— 20 mA sink/source current

• JTAG/EOnCE debug programming interface for real-time debugging

— IEEE 1149.1 Joint Test Action Group (JTAG) interface

— EOnCE interface for real-time debugging

6 Power Saving Features

• Three low power modes

— Low-speed run, wait, and stop modes: 200 kHz IP bus clock provided by ROSC

— Low-power run, wait, and stop modes: clock provided by external 32–38.4 kHz crystal

— Partial power down mode

• Low power external oscillator can be used in any low-power mode to provide accurate clock to active peripherals

• Low power real time counter for use in run, wait, and stop modes with internal and external clock sources

• 32 s typical wakeup time from partial power down modes

• Each peripheral can be individually disabled to save power

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56800E 56F8xxx Microcontroller IC 16-Bit 32MHz 32KB (16K x 16) FLASH 64-LQFP (10x10)

56F8037/56F8027 Description

The 56F8037/56F8027 is a member of the 56800E core-based family of Digital Signal Controllers (DSCs).

It combines, on a single chip, the processing power of a DSP and the functionality of a microcontroller

with a flexible set of peripherals to create an extremely cost-effective solution. Because of its low cost,

configuration flexibility, and compact program code, the 56F8037/56F8027 is well-suited for many

applications. The 56F8037/56F8027 includes many peripherals that are especially useful for industrial

control, motion control, home appliances, general purpose inverters, smart sensors, fire and security

systems, switched-mode power supply, power management, and medical monitoring applications.

The 56800E core is based on a dual Harvard-style architecture consisting of three execution units

operating in parallel, allowing as many as six operations per instruction cycle. The MCU-style

programming model and optimized instruction set allow straightforward generation of efficient, compact

DSP and control code. The instruction set is also highly efficient for C compilers to enable rapid

development of optimized control applications.

The 56F8037/56F8027 supports program execution from internal memories. Two data operands can be

accessed from the on-chip data RAM per instruction cycle. The 56F8037/56F8027 also offers up to 53

General Purpose Input/Output (GPIO) lines, depending on peripheral configuration.

The 56F8037 Digital Signal Controller includes 64KB of Program Flash and 8KB of Unified

Data/Program RAM. The 56F8027 Digital Signal Controller includes 32KB of Program Flash and 4KB of

Unified Data/Program RAM. Program Flash memory can be independently bulk erased or erased in pages.

Program Flash page erase size is 512 Bytes (256 Words).

A full set of programmable peripherals—PWM, ADCs, QSCIs, QSPIs, I2C, PITs, Quad Timers, DACs

and analog comparators—supports various applications. Each peripheral can be independently shut down

to save power. Any pin in these peripherals can also be used as General Purpose Input/Outputs (GPIOs).

56F8037/56F8027 Features

Digital Signal Controller Core

• Efficient 16-bit 56800E family Digital Signal Controller (DSC) engine with dual Harvard architecture

• As many as 32 Million Instructions Per Second (MIPS) at 32MHz core frequency

• Single-cycle 16  16-bit parallel Multiplier-Accumulator (MAC)

• Four 36-bit accumulators, including extension bits

• 32-bit arithmetic and logic multi-bit shifter

• Parallel instruction set with unique DSP addressing modes

• Hardware DO and REP loops

• Three internal address buses

• Four internal data buses

• Instruction set supports both DSP and controller functions

• Controller-style addressing modes and instructions for compact code

• Efficient C compiler and local variable support

• Software subroutine and interrupt stack with depth limited only by memory

• JTAG/Enhanced On-Chip Emulation (OnCE) for unobtrusive, processor speed-independent, real-time 

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