NXP USA Inc.

56800 56F8xx Microcontroller IC 16-Bit 80MHz 64KB (32K x 16) FLASH 100-LQFP (14x14)

Overview 

56F803 Description

The 56F803 is a member of the 56800 core-based family of processors. It combines, on a single chip, the processing power of a DSP and 

the functionality of a microcontroller with a flexible set of peripherals to create an extremely cost-effective solution. Because of its low 

cost, configuration flexibility, and compactprogram code, the 56F803 is well-suited for many applications. The 56F803 includes many 

peripherals that are especially useful for applications such as motion control, smart appliances, steppers, encoders, tachometers, limit

switches, power supply and control, automotive control, engine management, noise suppression, remote utility metering, and industrial 

control for power, lighting, and automation.

The 56800 core is based on a Harvard-style architecture consisting of three execution units operating in parallel, allowing as many as 

six operations per instruction cycle. The MCU-style programming model and optimized instruction set allow straightforward generation

of efficient, compact device and control code. The instruction set is also highly efficient for C compilers to enable rapid development of 

optimized control applications.

The 56F803 supports program execution from either internal or external memories. Two data operands can be accessed from the

on-chip Data RAM per instruction cycle. The 56F803 also provides two external dedicated interrupt lines, and up to 16 General Purpose 

Input/Output (GPIO) lines, depending on peripheral configuration.The 56F803 controller includes 31.5K words (16-bit) of Program 

Flash and 4K words of Data Flash (each programmable through the JTAG port) with 512 words of Program RAM and 2K words of Data 

RAM. It also supports program execution from external memory.

A total of 2K words of Boot Flash is incorporated for easy customer-inclusion of field-programmable software routines that can be used 

to program the main Program and Data Flash memory areas. Both Program and Data Flash memories can be independently 

bulk–erased or erased in page sizes of 256 words. The Boot Flash memory can also be either bulk- or page-erased.

A key application-specific feature of the 56F803 is the inclusion of a Pulse Width Modulator (PWM) module. This module incorporates 

three complementary, individually programmable PWM signal outputs (the module is also capable of supporting three independent 

PWM functions, for a total of six PWM outputs) to enhance motor control functionality. Complementary operation permits 

programmable dead time insertion, distortion correction via current sensing by software, and separate top and bottom output polarity 

control. The up-counter value is programmable to support a continuously variable PWM frequency. Edge- and center-aligned 

synchronous pulse width control (0% to 100% modulation) is supported. The device is capable of controlling most motor types: ACIM 

(AC Induction Motors), both BDC and BLDC (Brush and Brushless DC motors), SRM and VRM (Switched and Variable Reluctance Motors), 

and stepper motors. The PWM incorporates fault protection and cycle-by-cycle current limiting with sufficient output drive capability to 

directly drive standard opto-isolators. A “smoke-inhibit”, write-once protection feature for key parameters and patented PWM 

waveform distortion correction circuit are also provided. The PWM is double-buffered and includes interrupt controls to permit integral 

reload rates to be programmable from 1 to 16. The PWM module provides a reference output to synchronize the ADC.

The 56F803 incorporates a separate Quadrature Decoder capable of capturing all four transitions on the two-phase inputs, permitting 

generation of a number proportional to actual position. Speed computation capabilities accommodate both fast and slow moving shafts. 

The integrated watchdog timer in the Quadrature Decoder can be programmed with a time-out value to alarm when no shaft motion is 

detected. Each input is filtered to ensure only true transitions are recorded.

This controller also provides a full set of standard programmable peripherals that include a Serial Communications Interface (SCI), one 

Serial Peripheral Interface (SPI), and four Quad Timers. Any of these interfaces can be used as General Purpose Input/Outputs (GPIO) if 

that function is not required. A Controller Area Network interface (CAN Version 2.0 A/B-compliant) and an internal interrupt controller 

are also included on the 56F803.

56F803 Features

 Processing Core

• Efficient 16-bit 56800 family controller engine with dual Harvard architecture

• As many as 40 Million Instructions Per Second (MIPS) at 80MHz core frequency

• Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC)

• Two 36-bit accumulators, including extension bits

• 16-bit bidirectional barrel shifter

• Parallel instruction set with unique processor addressing modes

• Hardware DO and REP loops

• Three internal address buses and one external address bus

• Four internal data buses and one external data bus

• Instruction set supports both DSP and controller functions

• Controller style addressing modes and instructions for compact code

• Efficient C compiler and local variable support

• Software subroutine and interrupt stack with depth limited only by memory

• JTAG/OnCE debug programming interface

Memory

• Harvard architecture permits as many as three simultaneous accesses to Program and Data memory

• On-chip memory including a low-cost, high-volume Flash solution

— 31.5K × 16-bit words of Program Flash

— 512K × 16-bit words of Program RAM

— 4K × 16-bit words of Data Flash

— 2K × 16-bit words of Data RAM

— 2K × 16-bit words of Boot Flash

• Off-chip memory expansion capabilities programmable for 0, 4, 8, or 12 wait states

— As much as 64K × 16 bits of Data memory

— As much as 64K × 16 bits of Program memory Peripheral Circuits for 56F803

Peripheral Circuits for 56F803

• Pulse Width Modulator module (PWM) with six PWM outputs, three Current Sense inputs, and three Fault inputs, fault-tolerant 

design with dead time insertion, supports both center- and edge- aligned modes, supports Freescale’s patented dead time 

distortion correction

• Two 12-bit Analog-to-Digital Converters (ADCs), which support two simultaneous conversions; ADC and PWM modules can be 

synchronized

• Quadrature Decoder with four inputs (shares pins with Quad Timer)

• Four General Purpose Quad Timers: Timer A (sharing pins with Quad Dec0), Timers B &C without external pins and Timer D with two pins

• CAN 2.0 B module with 2-pin ports for transmit and receive

• Serial Communication Interface (SCI) with two pins (or two additional GPIO lines)

• Serial Peripheral Interface (SPI) with configurable 4-pin port (or four additional GPIO lines)

• Computer Operating Properly (COP) Watchdog timer

• Two dedicated external interrupt pins

• Sixteen multiplexed General Purpose I/O (GPIO) pins

• External reset input pin for hardware reset

• JTAG/On-Chip Emulation (OnCE™) for unobtrusive, processor speed-independent debugging

• Software-programmable, Phase Locked Loop-based frequency synthesizer for the controller core clock

Energy Information

• Fabricated in high-density CMOS with 5V-tolerant, TTL-compatible digital inputs

• Uses a single 3.3V power supply

• On-chip regulators for digital and analog circuitry to lower cost and reduce noise

• Wait and Stop modes available

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12V1 HCS12 Microcontroller IC 16-Bit 25MHz 128KB (128K x 8) FLASH 64-LQFP (10x10)

Introduction

The MC9S12G-Family is an optimized, automotive, 16-bit microcontroller product line focused on

low-cost, high-performance, and low pin-count. This family is intended to bridge between high-end 8-bit

microcontrollers and high-performance 16-bit microcontrollers, such as the MC9S12XS-Family. The

MC9S12G-Family is targeted at generic automotive applications requiring CAN or LIN/J2602

communication. Typical examples of these applications include body controllers, occupant detection, door

modules, seat controllers, RKE receivers, smart actuators, lighting modules, and smart junction boxes.

The MC9S12G-Family uses many of the same features found on the MC9S12XS- and MC9S12P-Family,

including error correction code (ECC) on flash memory, a fast analog-to-digital converter (ADC) and a

frequency modulated phase locked loop (IPLL) that improves the EMC performance. 

The MC9S12G-Family is optimized for lower program memory sizes down to 16k. In order to simplify

customer use it features an EEPROM with a small 4 bytes erase sector size.

The MC9S12G-Family deliver all the advantages and efficiencies of a 16-bit MCU while retaining the low

cost, power consumption, EMC, and code-size efficiency advantages currently enjoyed by users of NXP’s

existing 8-bit and 16-bit MCU families. Like the MC9S12XS-Family, the MC9S12G-Family run 16-bit

wide accesses without wait states for all peripherals and memories. The MC9S12G-Family is available in

100-pin LQFP, 64-pin LQFP, 48-pin LQFP/QFN, 32-pin LQFP and 20-pin TSSOP package options and

aims to maximize the amount of functionality especially for the lower pin count packages. In addition to

the I/O ports available in each module, further I/O ports are available with interrupt capability allowing

wake-up from stop or wait modes.

Chip-Level Features

On-chip modules available within the family include the following features:

• S12 CPU core

• Up to 240 Kbyte on-chip flash with ECC

• Up to 4 Kbyte EEPROM with ECC

• Up to 11 Kbyte on-chip SRAM

• Phase locked loop (IPLL) frequency multiplier with internal filter

• 4–16 MHz amplitude controlled Pierce oscillator

• 1 MHz internal RC oscillator

• Timer module (TIM) supporting up to eight channels that provide a range of 16-bit input capture,

output compare, counter, and pulse accumulator functions

• Pulse width modulation (PWM) module with up to eight x 8-bit channels

• Up to 16-channel, 10 or 12-bit resolution successive approximation analog-to-digital converter

(ADC)

• Up to two 8-bit digital-to-analog converters (DAC)

• Up to one 5V analog comparator (ACMP)

• Up to three serial peripheral interface (SPI) modules

• Up to three serial communication interface (SCI) modules supporting LIN communications

• Up to one multi-scalable controller area network (MSCAN) module (supporting CAN protocol

2.0A/B)

• On-chip voltage regulator (VREG) for regulation of input supply and all internal voltages

• Autonomous periodic interrupt (API)

• Precision fixed voltage reference for ADC conversions

• Optional reference voltage attenuator module to increase ADC accuracy

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