NXP USA Inc.

HCS12 HCS12 Microcontroller IC 16-Bit 25MHz 64KB (64K x 8) FLASH 48-LQFP (7x7)

Overview 

Device Introduction

The MC9S12C-Family / MC9S12GC-Family are 48/52/80 pin Flash-based MCU families, which deliver the power and flexibility of the 16-bit core to a whole new range of cost and space sensitive, general purpose industrial and automotive network applications. All MC9S12C-Family / MC9S12GC-Family members feature standard on-chip peripherals including a 16-bit central processing unit (CPU12), up to 128K bytes of Flash EEPROM, up to 4K bytes of RAM, an asynchronous serial communications interface

(SCI), a serial peripheral interface (SPI), an 8-channel 16-bit timer module (TIM), a 6-channel 8-bit pulse width modulator (PWM), an 8-channel, 10-bit analog-to-digital converter (ADC).

The MC9S12C128-Family members also feature a CAN 2.0 A, B software compatible module (MSCAN12).

All MC9S12C-Family / MC9S12GC-Family devices feature full 16-bit data paths throughout. The inclusion of a PLL circuit allows power consumption and performance to be adjusted to suit operational requirements. In addition to the I/O ports available in each module, up to 10 dedicated I/O port bits are available with wake-up capability from stop or wait mode. The devices are available in 48-, 52-, and 80-pin QFP packages, with the 80-pin version pin compatible to the HCS12 A, B, and D Family derivatives.

Device Features

• 16-bit HCS12 core:

— HCS12 CPU

– Upward compatible with M68HC11 instruction set

– Interrupt stacking and programmer’s model identical to M68HC11

– Instruction queue

– Enhanced indexed addressing

— MMC (memory map and interface)

— INT (interrupt control)

— BDM (background debug mode)

— DBG12 (enhanced debug12 module, including breakpoints and change-of-flow trace buffer)

— MEBI (multiplexed expansion bus interface) available only in 80-pin package version

• Wake-up interrupt inputs:

— Up to 12 port bits available for wake up interrupt function with digital filtering

• Memory options:

— 16K or 32Kbyte Flash EEPROM (erasable in 512-byte sectors)

64K, 96K, or 128Kbyte Flash EEPROM (erasable in 1024-byte sectors)

— 1K, 2K or 4K Byte RAM

• Analog-to-digital converters:

— One 8-channel module with 10-bit resolution

— External conversion trigger capability

• Available on MC9S12C Family:

— One 1M bit per second, CAN 2.0 A, B software compatible module

— Five receive and three transmit buffers

— Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit, or 8 x 8 bit

— Four separate interrupt channels for Rx, Tx, error, and wake-up

— Low-pass filter wake-up function

— Loop-back for self test operation

• Timer module (TIM):

— 8-channel timer

— Each channel configurable as either input capture or output compare

— Simple PWM mode

— Modulo reset of timer counter

— 16-bit pulse accumulator

— External event counting

— Gated time accumulation

• PWM module:

— Programmable period and duty cycle

— 8-bit 6-channel or 16-bit 3-channel

— Separate control for each pulse width and duty cycle

— Center-aligned or left-aligned outputs

— Programmable clock select logic with a wide range of frequencies

— Fast emergency shutdown input

• Serial interfaces:

— One asynchronous serial communications interface (SCI)

— One synchronous serial peripheral interface (SPI)

• CRG (clock reset generator module)

— Windowed COP watchdog

— Real time interrupt

— Clock monitor

— Pierce or low current Colpitts oscillator

— Phase-locked loop clock frequency multiplier

— Limp home mode in absence of external clock

— Low power 0.5MHz to 16MHz crystal oscillator reference clock

• Operating frequency:

— 32MHz equivalent to 16MHz bus speed for single chip

— 32MHz equivalent to 16MHz bus speed in expanded bus modes

— Option of 9S12C Family: 50MHz equivalent to 25MHz bus speed

— All 9S12GC Family members allow a 50MHz operating frequency.

• Internal 2.5V regulator:

— Supports an input voltage range from 2.97V to 5.5V

— Low power mode capability

— Includes low voltage reset (LVR) circuitry

— Includes low voltage interrupt (LVI) circuitry

• 48-pin LQFP, 52-pin LQFP, or 80-pin QFP package:

— Up to 58 I/O lines with 5V input and drive capability (80-pin package)

— Up to 2 dedicated 5V input only lines (IRQ, XIRQ)

— 5V 8 A/D converter inputs and 5V I/O

• Development support:

— Single-wire background debug™ mode (BDM)

— On-chip hardware breakpoints

— Enhanced DBG12 debug features

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56800E 56F8xxx Microcontroller IC 16-Bit 60MHz 512KB (256K x 16) FLASH 160-LQFP (24x24)

Device Description

The 56F8366 and 56F8166 are members of the 56800E core-based family of controllers. Each combines,

on a single chip, the processing power of a Digital Signal Processor (DSP) and the functionality of a

microcontroller with a flexible set of peripherals to create an extremely cost-effective solution. Because

of its low cost, configuration flexibility, and compact program code, the 56F8366 and 56F8166 are

well-suited for many applications. The devices include many peripherals that are especially useful for

motion control, smart appliances, steppers, encoders, tachometers, limit switches, power supply and

control, automotive control (56F8366 only), engine management, noise suppression, remote utility

metering, industrial control for power, lighting, and automation applications.

The 56800E core is based on a Harvard-style architecture consisting of three execution units operating in

parallel, allowing as many as six operations per instruction cycle. The MCU-style programming model and

optimized instruction set allow straightforward generation of efficient, compact DSP and control code.

The instruction set is also highly efficient for C/C++ Compilers to enable rapid development of optimized

control applications.

The 56F8366 and 56F8166 support program execution from either internal or external memories. Two

data operands can be accessed from the on-chip data RAM per instruction cycle. These devices also

provides two external dedicated interrupt lines and up to 62 General Purpose Input/Output (GPIO) lines,

depending on peripheral configuration.

56F8366 Features

The 56F8366 hybrid controller includes 512KB of Program Flash and 32KB of Data Flash (each

programmable through the JTAG port) with 4KB of Program RAM and 32KB of Data RAM. It also

supports program execution from external memory.

A total of 32KB of Boot Flash is incorporated for easy customer inclusion of field-programmable software

routines that can be used to program the main Program and Data Flash memory areas. Both Program and

Data Flash memories can be independently bulk erased or erased in pages. Program Flash page erase size

is 1KB. Boot and Data Flash page erase size is 512 bytes. The Boot Flash memory can also be either bulk

or page erased.

A key application-specific feature of the 56F8366 is the inclusion of two Pulse Width Modulator (PWM)

modules. These modules each incorporate three complementary, individually programmable PWM signal

output pairs (each module is also capable of supporting six independent PWM functions, for a total of 12

PWM outputs) to enhance motor control functionality. Complementary operation permits programmable

dead time insertion, distortion correction via current sensing by software, and separate top and bottom

output polarity control. The up-counter value is programmable to support a continuously variable PWM

frequency. Edge-aligned and center-aligned synchronous pulse width control (0% to 100% modulation) is

supported. The device is capable of controlling most motor types: ACIM (AC Induction Motors); both

BDC and BLDC (Brush and Brushless DC motors); SRM and VRM (Switched and Variable Reluctance

Motors); and stepper motors. The PWMs incorporate fault protection and cycle-by-cycle current limiting

with sufficient output drive capability to directly drive standard optoisolators. A “smoke-inhibit”,

write-once protection feature for key parameters is also included. A patented PWM waveform distortion

correction circuit is also provided. Each PWM is double-buffered and includes interrupt controls to permit

integral reload rates to be programmable from 1 to 16. The PWM modules provide reference outputs to

synchronize the Analog-to-Digital Converters through two channels of Quad Timer C.

The 56F8366 incorporates two Quadrature Decoders capable of capturing all four transitions on the

two-phase inputs, permitting generation of a number proportional to actual position. Speed computation

capabilities accommodate both fast- and slow-moving shafts. An integrated watchdog timer in the

Quadrature Decoder can be programmed with a time-out value to alert when no shaft motion is detected.

Each input is filtered to ensure only true transitions are recorded.

This controller also provides a full set of standard programmable peripherals that include two Serial

Communications Interfaces (SCIs), two Serial Peripheral Interfaces (SPIs), and four Quad Timers. Any of

these interfaces can be used as General-Purpose Input/Outputs (GPIOs) if that function is not required.

Two Flex Controller Area Network (FlexCAN) interfaces (CAN Version 2.0 B-compliant) and an internal

interrupt controller are included on the 56F8366.