NXP USA Inc.

56800E 56F8xxx Microcontroller IC 16-Bit 32MHz 16KB (8K x 16) FLASH 32-LQFP (7x7)

Overview

This document provides an overview of the major features and functional components of the 

MC56F8006/MC56F8002 series of digital signal controllers (DSCs).

The devices in the MC56F8006/MC56F8002 series combine, on a single chip, the processing power of a 

digital signal processor (DSP) and the functionality of a microcontroller unit (MCU) with a flexible set of peripherals 

to create an extremely cost-effective solution.

The MC56F8006/MC56F8002 uses the 56800E core, which is based on a dual Harvard-style architecture consisting of 

three execution units operating in parallel. This allows as many as six operations per instruction cycle. The MCU-style 

programming model and optimized instruction set allow straightforward generation of efficient, compact DSP and 

control code. The instruction set is also highly efficient for C compilers to enable rapid development of optimized 

control applications.

A full set of programmable peripherals supports various applications. Any signal pin associated with these peripherals can also 

be used for general-purpose input/output (GPIO). Power-saving features include an extremely low-power mode and the ability 

to shut down each peripheral independently.

56F8006/56F8002 Features

1.Core

• Efficient 16-bit 56800E family digital signal controller (DSC) engine with dual Harvard architecture

• As many as 32 million instructions per second (MIPS) at 32 MHz core frequency

• 155 basic instructions in conjunction with up to 20 address modes

• Single-cycle 16  16-bit parallel multiplier-accumulator (MAC)

• Four 36-bit accumulators, including extension bits

• 32-bit arithmetic and logic multi-bit shifter

• Parallel instruction set with unique DSP addressing modes

• Hardware DO and REP loops

• Three internal address buses

• Four internal data buses

• Instruction set supports DSP and controller functions

• Controller-style addressing modes and instructions for compact code

• Efficient C compiler and local variable support

• Software subroutine and interrupt stack with depth limited only by memory

• JTAG/enhanced on-chip emulation (EOnCE) for unobtrusive, processor speed–independent, real-time debugging

2.Operation Range

• 1.8 V to 3.6 V operation (power supplies and I/O)

• From power-on-reset: approximately 1.9 V to 3.6 V

• Ambient temperature operating range:

— –40 °C to 125 °C

3.Memory

• Dual Harvard architecture permits as many as three simultaneous accesses to program and data memory

• Flash security and protection that prevent unauthorized users from gaining access to the internal flash

• On-chip memory

— 16 KB of program flash for 56F8006 and 12 KB of program flash for 56F8002

— 2 KB of unified data/program RAM

• EEPROM emulation capability using flash

4.Interrupt Controller

• Five interrupt priority levels

— Three user programmable priority levels for each interrupt source: Level 0, 1, 2

— Unmaskable level 3 interrupts include: illegal instruction, hardware stack overflow, misaligned data access, SWI3

instruction. Maskable level 3 interrupts include: EOnCE step counter, EOnCE breakpoint unit, EOnCE trace

buffer

— Lowest-priority software interrupt: level LP

• Allow nested interrupt that higher priority level interrupt request can interrupt lower priority interrupt subroutine

• The masking of interrupt priority level is managed by the 56800E core

• One programmable fast interrupt that can be assigned to any interrupt source

• Notification to system integration module (SIM) to restart clock out of wait and stop states

• Ability to relocate interrupt vector table

5.Peripheral Highlights

• One multi-function, six-output pulse width modulator (PWM) module

— Up to 96 MHz PWM operating clock

— 15 bits of resolution

— Center-aligned and edge-aligned PWM signal mode

— Phase shifting PWM pulse generation

— Four programmable fault inputs with programmable digital filter

— Double-buffered PWM registers

— Separate deadtime insertions for rising and falling edges

— Separate top and bottom pulse-width correction by means of software

— Asymmetric PWM output within both Center Aligned and Edge Aligned operation

— Separate top and bottom polarity control

— Each complementary PWM signal pair allows selection of a PWM supply source from:

– PWM generator

– Internal timers

– Analog comparator outputs

• Two independent 12-bit analog-to-digital converters (ADCs)

— 2 x 14 channel external inputs plus seven internal inputs

— Support simultaneous and software triggering conversions

— ADC conversions can be synchronized by PWM and PDB modules

— Sampling rate up to 400 KSPS for 10- or 12-bit conversion result; 470 KSPS for 8-bit conversion result

— Two 16-word result registers

• Two programmable gain amplifier (PGAs)

— Each PGA is designed to amplify and convert differential signals to a single-ended value fed to one of the ADC

inputs

— 1X, 2X, 4X, 8X, 16X, or 32X gain

— Software and hardware triggers are available

— Integrated sample/hold circuit

— Includes additional calibration features:

– Offset calibration eliminates any errors in the internal reference used to generate the VDDA/2 output center

point

– Gain calibration can be used to verify the gain of the overall datapath

– Both features require software correction of the ADC result

• Three analog comparators (CMPs)

— Selectable input source includes external pins, internal DACs

— Programmable output polarity

— Output can drive timer input, PWM fault input, PWM source, external pin output, and trigger ADCs

— Output falling and rising edge detection able to generate interrupts

• One dual channel 16-bit multi-purpose timer module (TMR)

— Two independent 16-bit counter/timers with cascading capability

— Up to 96 MHz operating clock

— Each timer has capture and compare and quadrature decoder capability

— Up to 12 operating modes

— Four external inputs and two external outputs

• One serial communication interface (SCI) with LIN slave functionality

— Up to 96 MHz operating clock

— Full-duplex or single-wire operation

— Programmable 8- or 9- bit data format

— Two receiver wakeup methods:

– Idle line

– Address mark

— 1/16 bit-time noise detection

• One serial peripheral interface (SPI)

— Full-duplex operation

— Master and slave modes

— Programmable length transactions (2 to 16 bits)

— Programmable transmit and receive shift order (MSB as first or last bit transmitted)

— Maximum slave module frequency = module clock frequency/2

• One inter-integrated Circuit (I2C) port

— Operates up to 400 kbps

— Supports master and slave operation

— Supports 10-bit address mode and broadcasting mode

— Supports SMBus, Version 2

• One 16-bit programmable interval timer (PIT)

— 16 bit counter with programmable counter modulo

— Interrupt capability

• One 16-bit programmable delay block (PDB)

— 16 bit counter with programmable counter modulo and delay time

— Counter is initiated by positive transition of internal or external trigger pulse

— Supports two independently controlled delay pulses used to synchronize PGA and ADC conversions with input

trigger event

— Two PDB outputs can be ORed together to schedule two conversions from one input trigger event

— PDB outputs can be can be used to schedule precise edge placement for a pulsed output that generates the control

signal for the CMP windowing comparison

— Supports continuous or single shot mode

— Bypass mode supported

• Computer operating properly (COP)/watchdog timer capable of selecting different clock sources

— Programmable prescaler and timeout period

— Programmable wait, stop, and partial powerdown mode operation

— Causes loss of reference reset 128 cycles after loss of reference clock to the PLL is detected

— Choice of clock sources from four sources in support of EN60730 and IEC61508:

– On-chip relaxation oscillator

– External crystal oscillator/external clock source

– System clock (IPBus up to 32 MHz)

– On-chip low power 1 kHz oscillator

• Real-timer counter (RTC)

— 8-bit up-counter

— Three software selectable clock sources

– External crystal oscillator/external clock source

– On-chip low-power 1 kHz oscillator

– System bus (IPBus up to 32 MHz)

— Can signal the device to exit power down mode

• Phase lock loop (PLL) provides a high-speed clock to the core and peripherals

— Provides 3x system clock to PWM and dual timer and SCI

— Loss of lock interrupt

— Loss of reference clock interrupt

• Clock sources

— On-chip relaxation oscillator with two user selectable frequencies: 400 kHz for low speed mode, 8 MHz for

normal operation

— On-chip low-power 1 kHz oscillator can be selected as clock source to the RTC and/or COP

— External clock: crystal oscillator, ceramic resonator, and external clock source

• Power management controller (PMC)

— On-chip regulator for digital and analog circuitry to lower cost and reduce noise

— Integrated power-on reset (POR)

— Low-voltage interrupt with a user selectable trip voltage of 1.81 V or 2.31 V

— User selectable brown-out reset

— Run, wait, and stop modes

— Low-power run, wait, and stop modes

— Partial power down mode

• Up to 40 general-purpose I/O (GPIO) pins

— Individual control for each pin to be in peripheral or GPIO mode

— Individual input/output direction control for each pin in GPIO mode

— Hysteresis and configurable pullup device on all input pins

— Configurable slew rate and drive strength and optional input low pass filters on all output pins

— 20 mA sink/source current

• JTAG/EOnCE debug programming interface for real-time debugging

— IEEE 1149.1 Joint Test Action Group (JTAG) interface

— EOnCE interface for real-time debugging

6.Power Saving Features

• Three low power modes

— Low-speed run, wait, and stop modes: 200 kHz IP bus clock provided by ROSC

— Low-power run, wait, and stop modes: clock provided by external 32–38.4 kHz crystal

— Partial power down mode

• Low power external oscillator can be used in any low-power mode to provide accurate clock to active peripherals

• Low power real time counter for use in run, wait, and stop modes with internal and external clock sources

• 32 s typical wakeup time from partial power down modes

• Each peripheral can be individually disabled to save power

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HCS12X HCS12X Microcontroller IC 16-Bit 50MHz 1MB (1M x 8) FLASH 112-LQFP (20x20)

Introduction

The new MC9S12XE Family of microcontrollers takes the innovation of today’s MC9S12XD Family a step further with

the introduction of new features to deliver enhanced system integrity and greater functionality. These new features include

a Memory Protection Unit (MPU) and Error Correction Code (ECC) on the Flash memory together with enhanced

EEPROM functionality (EEE), an enhanced XGATE, a Frequency Modulated Phase Locked Loop (IPLL) and a faster

ATD. The E Family will extend the S12X product range up to 1MB of Flash memory with increased I/O capability in the

208-pin version of the flagship MC9S12XEP100.

Targeted at automotive multiplexing and generic auto body applications, S12XE Family will deliver 32-bit performance

with all the advantages and efficiencies of a 16-bit MCU. It will retain the low cost, power consumption, EMC and codesize

efficiency advantages currently enjoyed by users of Freescale’s existing 16-bit S12 and S12X MCU families.

There is a high level of compatibility between the S12XE and S12XD families.

Like members of other S12X families, the S12XE Family will run 16-bit wide accesses without wait states for all peripherals

and memories.

The S12XE Family features an enhanced version of the performance-boosting XGATE co-processor which is

programmable in “C” language and runs at twice the bus frequency of the S12X with an instruction set optimized for

data movement, logic and bit manipulation instructions and which can service any peripheral module on the device. The new

enhanced version has improved interrupt handling capability and is fully compatible with existing XGATE module.

As with the S12XD Family, the S12XE Family features an enhanced MSCAN module which, when used in conjunction with

XGATE, delivers FULL CAN performance with virtually unlimited number of mailboxes and retains backwards

compatibility with the MSCAN module featured on existing S12 products.

The S12XE Family has full 16-bit data paths throughout. The non-multiplexed expanded bus interface available on the 144-

pin versions allows an easy interface to external memories. In addition to the I/O ports available in each module, up to 25

further I/O ports are available with interrupt capability allowing wake-up from STOP orWAIT mode. The S12XE Family is

available in 208-Pin MAPBGA, 144-pin LQFP (both with optional external bus), 112-pin LQFP or 80-Pin QFP options.

Chip-Level Features

• Pin compatible family extends existing S12D Family

• 16-bit CPU12X

• Enables higher system integrity at the MCU level (MPU, ECC, Supervisor Mode)

• Enhanced SPI allows 8 or 16 bit data size

• ECC on flash

• 1-bit fault correction

• 2-bit fault detection

• Improved EMC performance

• Separate supply for internal voltage regulator and I/O allow optimized EMC filtering

• Enhanced current consumption

• Extended API up to 5 sec

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HCS12X HCS12X Microcontroller IC 16-Bit 40MHz 128KB (128K x 8) FLASH 112-LQFP (20x20)

MC9S12XS256

Covers MC9S12XS Family

MC9S12XS256

MC9S12XS128

MC9S12XS64

Introduction

The new S12XS family of 16-bit micro controllers is a compatible, reduced version of the S12XE family.

These families provide an easy approach to develop common platforms from low-end to high-end

applications, minimizing the redesign of software and hardware.

Targeted at generic automotive applications and CAN nodes, some typical examples of these applications

are: Body Controllers, Occupant Detection, Door Modules, RKE Receivers, Smart Actuators, Lighting

Modules and Smart Junction Boxes amongst many others.

The S12XS family retains many of the features of the S12XE family including Error Correction Code

(ECC) on Flash memory, a separate Data-Flash Module for code or data storage, a Frequency Modulated

Locked Loop (IPLL) that improves the EMC performance and a fast ATD converter.

S12XS family delivers 32-bit performance with all the advantages and efficiencies of a 16-bit MCU while

retaining the low cost, power consumption, EMC and code-size efficiency advantages currently enjoyed

by users of Freescale’s existing 16-bit S12 and S12X MCU families. Like members of other S12X

families, the S12XS family runs 16-bit wide accesses without wait states for all peripherals and memories.

The S12XS family is available in 112-pin LQFP, 80-pin QFP, 64-pin LQFP package options and maintains

a high level of pin compatibility with the S12XE family. In addition to the I/O ports available in each

module, up to 18 further I/O ports are available with interrupt capability allowing Wake-Up from stop or

wait modes.

The peripheral set includes MSCAN, SPI, two SCIs, an 8-channel 24-bit periodic interrupt timer, 8-

channel 16-bit Timer, 8-channel PWM and up to 16- channel 12-bit ATD converter.

Software controlled peripheral-to-port routing enables access to a flexible mix of the peripheral modules

in the lower pin count package options.

Features

• 16-bit CPU12X

— Upward compatible with S12 instruction set with the exception of five Fuzzy instructions

(MEM, WAV, WAVR, REV, REVW) which have been removed

— Enhanced indexed addressing

— Access to large data segments independent of PPAGE

• INT (interrupt module)

— Seven levels of nested interrupts

— Flexible assignment of interrupt sources to each interrupt level.

— External non-maskable high priority interrupt (XIRQ)

— The following inputs can act as Wake-up Interrupts

– IRQ and non-maskable XIRQ

– CAN receive pins

– SCI receive pins

– Depending on the package option up to 20 pins on ports J, H and P configurable as rising or

falling edge sensitive

• MMC (module mapping control)

• DBG (debug module)

— Monitoring of CPU bus with tag-type or force-type breakpoint requests

— 64 x 64-bit circular trace buffer captures change-of-flow or memory access information

• BDM (background debug mode)

• OSC_LCP (oscillator)

— Low power loop control Pierce oscillator utilizing a 4MHz to 16MHz crystal

— Good noise immunity

— Full-swing Pierce option utilizing a 2MHz to 40MHz crystal

— Transconductance sized for optimum start-up margin for typical crystals

• IPLL (Internally filtered, frequency modulated phase-locked-loop clock generation)

— No external components required

— Configurable option to spread spectrum for reduced EMC radiation (frequency modulation)

• CRG (clock and reset generation)

— COP watchdog

— Real time interrupt

— Clock monitor

— Fast wake up from STOP in self clock mode

• Memory Options

— 64, 128 and 256 Kbyte Flash

— Flash General Features

– 64 data bits plus 8 syndrome ECC (Error Correction Code) bits allow single bit failure

correction and double fault detection

– Erase sector size 1024 bytes

– Automated program and erase algorithm

– Protection scheme to prevent accidental program or erase

– Security option to prevent unauthorized access

– Sense-amp margin level setting for reads

— 4 and 8 Kbyte Data Flash space

– 16 data bits plus 6 syndrome ECC (Error Correction Code) bits allow single bit failure

correction and double fault detection

– Erase sector size 256 bytes

– Automated program and erase algorithm

— 4, 8 and 12 Kbyte RAM

• 16-channel, 12-bit Analog-to-Digital converter

— 8/10/12 Bit resolution

— 3µs, 10-bit single conversion time

— Left or right justified result data

— External and internal conversion trigger capability

— Internal oscillator for conversion in Stop modes

— Wake from low power modes on analog comparison > or <= match

— Continuous conversion mode

— Multiplexer for 16 analog input channels

— Multiple channel scans

— Pins can also be used as digital I/O

• MSCAN (1 M bit per second, CAN 2.0 A, B software compatible module)

— 1 Mbit per second, CAN 2.0 A, B software compatible module

– Standard and extended data frames

– 0 - 8 bytes data length

– Programmable bit rate up to 1 Mbps

— Five receive buffers with FIFO storage scheme

— Three transmit buffers with internal prioritization

— Flexible identifier acceptance filter programmable as:

– 2 x 32-bit

– 4 x 16-bit

– 8 x 8-bit

— Wake-up with integrated low pass filter option

— Loop back for self test

— Listen-only mode to monitor CAN bus

— Bus-off recovery by software intervention or automatically

— 16-bit time stamp of transmitted/received messages

• TIM (standard timer module)

— 8 x 16-bit channels for input capture or output compare

— 16-bit free-running counter with 8-bit precision prescaler

— 1 x 16-bit pulse accumulator

• PIT (periodic interrupt timer)

— Up to four timers with independent time-out periods

— Time-out periods selectable between 1 and 224 bus clock cycles

— Time-out interrupt and peripheral triggers

— Start of timers can be aligned

• Up to 8 channel x 8-bit or 4 channel x 16-bit Pulse Width Modulator

— Programmable period and duty cycle per channel

— Center- or left-aligned outputs

— Programmable clock select logic with a wide range of frequencies

• Serial Peripheral Interface Module (SPI)

— Configurable for 8 or 16-bit data size

— Full-duplex or single-wire bidirectional

— Double-buffered transmit and receive

— Master or Slave mode

— MSB-first or LSB-first shifting

— Serial clock phase and polarity options

• Two Serial Communication Interfaces (SCI)

— Full-duplex or single wire operation

— Standard mark/space non-return-to-zero (NRZ) format

— Selectable IrDA 1.4 return-to-zero-inverted (RZI) format with programmable pulse widths

— 13-bit baud rate selection

— Programmable character length

— Programmable polarity for transmitter and receiver

— Receive wakeup on active edge

— Break detect and transmit collision detect supporting LIN

• On-Chip Voltage Regulator

— Two parallel, linear voltage regulators with bandgap reference

— Low-voltage detect (LVD) with low-voltage interrupt (LVI)

— Power-on reset (POR) circuit

— Low-voltage reset (LVR)

• Low-power wake-up timer (API)

— Internal oscillator driving a down counter

— Trimmable to +/-5% accuracy

— Time-out periods range from 0.2ms to ~13s with a 0.2ms resolution

• Input/Output

— Up to 91 general-purpose input/output (I/O) pins depending on the package option and 2 inputonly

pins

— Hysteresis and configurable pull up/pull down device on all input pins

— Configurable drive strength on all output pins

• Package Options

— 112-pin low-profile quad flat-pack (LQFP)

— 80-pin quad flat-pack (QFP)

— 64-pin low-profile quad flat-pack (LQFP)

• Operating Conditions

— Wide single Supply Voltage range 3.135 V to 5.5 V at full performance

– Separate supply for internal voltage regulator and I/O allow optimized EMC filtering

— 40MHz maximum CPU bus frequency

— Ambient temperature range –40°C to 125°C

— Temperature Options:

– –40°C to 85°C

– –40°C to 105°C

– –40°C to 125°C