CPU12 HC12 Microcontroller IC 16-Bit 8MHz 128KB (128K x 8) FLASH 112-LQFP (20x20)

Introduction

The MC68HC912DT128A microcontroller unit (MCU) is a 16-bit device

composed of standard on-chip peripherals including a 16-bit central

processing unit (CPU12), 128K bytes of flash EEPROM, 8K bytes of

RAM, 2K bytes of EEPROM, two asynchronous serial communications

interfaces (SCI), a serial peripheral interface (SPI), an inter-IC interface

(I2C), an enhanced capture timer (ECT), two 8-channel, 10-bit analogto-digital

converters (ADC), a four-channel pulse-width modulator

(PWM), and three CAN 2.0 A, B software compatible modules

(MSCAN12). System resource mapping, clock generation, interrupt

control and bus interfacing are managed by the lite integration module

(LIM). The MC68HC912DT128A has full 16-bit data paths throughout,

however, the external bus can operate in an 8-bit narrow mode so single

8-bit wide memory can be interfaced for lower cost systems. The

inclusion of a PLL circuit allows power consumption and performance to

be adjusted to suit operational requirements. In addition to the I/O ports

available in each module, 16 I/O ports are available with Key-Wake-Up

capability from STOP or WAIT mode.

Features

• 16-bit CPU12

– Upward compatible with M68HC11 instruction set

– Interrupt stacking and programmer’s model identical to

M68HC11

– 20-bit ALU

– Instruction queue

– Enhanced indexed addressing

• Multiplexed bus

– Single chip or expanded

– 16 address/16 data wide or 16 address/8 data narrow modes

• Memory

– 128K byte flash EEPROM, made of four 32K byte modules

with 8K bytes protected BOOT section in each module

– 2K byte EEPROM

– 8K byte RAM with Vstby, made of two 4K byte modules.

• Two Analog-to-digital converters

– 2 times 8-channels, 10-bit resolution

• Three 1M bit per second, CAN 2.0 A, B software compatible

modules on the MC68HC912DT128A (two on the

MC68HC912DG128A)

– Two receive and three transmit buffers per CAN

– Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit or

8 x 8 bit

– Four separate interrupt channels for Rx, Tx, error and wake-up

per CAN

– Low-pass filter wake-up function

– Loop-back for self test operation

– Programmable link to a timer input capture channel, for timestamping

and network synchronization.

• Enhanced capture timer (ECT)

– 16-bit main counter with 7-bit prescaler

– 8 programmable input capture or output compare channels; 4

of the 8 input captures with buffer

– Input capture filters and buffers, three successive captures on

four channels, or two captures on four channels with a

capture/compare selectable on the remaining four

– Four 8-bit or two 16-bit pulse accumulators

– 16-bit modulus down-counter with 4-bit prescaler

– Four user-selectable delay counters for signal filtering

• 4 PWM channels with programmable period and duty cycle

– 8-bit 4-channel or 16-bit 2-channel

– Separate control for each pulse width and duty cycle

– Center- or left-aligned outputs

– Programmable clock select logic with a wide range of

frequencies

• Serial interfaces

– Two asynchronous serial communications interfaces (SCI)

– Inter IC bus interface (I2C)

– Synchronous serial peripheral interface (SPI)

• LIM (lite integration module)

– WCR (windowed COP watchdog, real time interrupt, clock

monitor)

– ROC (reset and clocks)

– MEBI (multiplexed external bus interface)

– MMI (memory map and interface)

– INT (interrupt control)

– BKP (breakpoints)

– BDM (background debug mode)

• Two 8-bit ports with key wake-up interrupt

• Clock generation

– Phase-locked loop clock frequency multiplier

– Limp home mode in absence of external clock

– Slow mode divider

– Low power 0.5 to 16 MHz crystal oscillator reference clock

– Option of a Pierce or Colpitts oscillator

• 112-Pin TQFP package

– Up to 67 general-purpose I/O lines on the

MC68HC912DT128A (up to 69 on the MC68HC912DG128A),

plus up to 18 input-only lines

– 5.0V operation at 8 MHz

• Development support

– Single-wire background debug™ mode (BDM)

– On-chip hardware breakpoints

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S12Z S12 MagniV Microcontroller IC 16-Bit 32MHz 32KB (32K x 8) FLASH 48-LQFP (7x7)

Introduction

The MC9S12ZVM-Family is an automotive 16-bit microcontroller family using the NVM + UHV

technology that offers the capability to integrate 40 V analog components. This family reuses many

features from the existing S12/S12X portfolio. The particular differentiating features of this family are the

enhanced S12Z core, the combination of dual-ADC synchronized with PWM generation and the

integration of “high-voltage” analog modules, including the voltage regulator (VREG), Gate Drive Unit

(GDU) and a Local Interconnect Network (LIN) physical layer. These features enable a fully integrated

single chip solution to drive up to 6 external power MOSFETs for BLDC or PMSM motor drive

applications.

The MC9S12ZVM-Family includes error correction code (ECC) on RAM and flash memory, EEPROM

for diagnostic or data storage, a fast analog-to-digital converter (ADC) and a frequency modulated phase

locked loop (IPLL) that improves the EMC performance. The MC9S12ZVM-Family delivers an

optimized solution with the integration of several key system components into a single device, optimizing

system architecture and achieving significant space savings. The MC9S12ZVM-Family delivers all the

advantages and efficiencies of a 16-bit MCU while retaining the low cost, power consumption, EMC, and

code-size efficiency advantages currently enjoyed by users of existing S12(X) families. The

MC9S12ZVM-Family is available in different pin-out options, using the 64-pin LQFP-EP and 48-pin

LQFP-EP packages to accommodate LIN, CAN and external PWM based application interfaces. In

addition to the I/O ports available in each module, further I/O ports are available with interrupt capability

allowing wake-up from stop or wait modes.

The MC9S12ZVM-Family is a general-purpose family of devices suitable for a range of applications,

including:

• 3-phase sensorless BLDC motor control for

— Fuel pump

— Water pump

— Oil pump

— A/C compressor

— HVAC blower

— Engine cooling fan

— Electric vehicle battery cooling fan

• Brush DC motor control requiring driving in 2 directions, along with PWM control for

— Reversible wiper

— Trunk opener

Chip-Level Features

On-chip modules available within the family include the following features:

• S12Z CPU core

• 128, 64, 32 or 16KB on-chip flash with ECC

• 512 or128 byte EEPROM with ECC

• 8, 4 or 2 KB on-chip SRAM with ECC

• Phase locked loop (IPLL) frequency multiplier with internal filter

• 1 MHz internal RC oscillator with +/-1.3% accuracy over rated temperature range

• 4-20MHz amplitude controlled pierce oscillator

• Internal COP (watchdog) module

• 6-channel, 15-bit pulse width modulator with fault protection (PMF) 

• Low side and high side FET pre-drivers for each phase

— Gate drive pre-regulator

— LDO (Low Dropout Voltage Regulator) (typically 11V)

— High side gate supply generated using bootstrap circuit with external diode and capacitor

— Sustaining charge pump with two external capacitors and diodes

— High side drain (HD) monitoring on internal ADC channel using HD/5 voltage

• Two parallel analog-to-digital converters (ADC) with 12-bit resolution and up to 9 channels

available on external pins

• Programmable Trigger Unit (PTU) for synchronization of PMF and ADC

• One serial peripheral interface (SPI) module

• One serial communication interface (SCI) module with interface to internal LIN physical layer

transceiver (with RX connected to a timer channel for frequency calibration purposes, if desired)

• Up to one additional SCI (not connected to LIN physical layer)

• On-chip LIN physical layer transceiver fully compliant with the LIN 2.2 standard

(S12ZVML versions)

• One High Voltage physical interface. (S12ZVM32, S12ZVM16 versions only)

• 4-channel timer module (TIM) with input capture/output compare

• MSCAN (1 Mbit/s, CAN 2.0 A, B software compatible) module

• On-chip voltage regulator (VREG) for regulation of input supply and all internal voltages

— Optional VREG ballast control output to supply an external CAN physical layer

• Two current sense circuits for overcurrent detection or torque measurement

• Autonomous periodic interrupt (API)

• 20mA high-current output for use as Hall sensor supply

• Supply voltage sense with low battery warning

• Chip temperature sensor

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HCS12 HCS12 Microcontroller IC 16-Bit 25MHz 32KB (32K x 8) FLASH 80-QFP (14x14)

MC9S12DJ64

Covers also

MC9S12D64, MC9S12A64, 

MC9S12D32,MC9S12A32

Overview

The MC9S12DJ64 microcontroller unit (MCU) is a 16-bit device composed of standard on-chip

peripherals including a 16-bit central processing unit (HCS12 CPU), 64K bytes of Flash EEPROM, 4K

bytes of RAM, 1K bytes of EEPROM, two asynchronous serial communications interfaces (SCI), one

serial peripheral interfaces (SPI), an 8-channel IC/OC enhanced capture timer, two 8-channel, 10-bit

analog-to-digital converters (ADC), an 8-channel pulse-width modulator (PWM), a digital Byte Data Link

Controller (BDLC), 29 discrete digital I/O channels (Port A, Port B, Port K and Port E), 20 discrete digital

I/O lines with interrupt and wakeup capability, a CAN 2.0 A, B software compatible modules

(MSCAN12), and an Inter-IC Bus. The MC9S12DJ64 has full 16-bit data paths throughout. However, the

external bus can operate in an 8-bit narrow mode so single 8-bit wide memory can be interfaced for lower

cost systems. The inclusion of a PLL circuit allows power consumption and performance to be adjusted to

suit operational requirements.

Features

• HCS12 Core

– 16-bit HCS12 CPU

i. Upward compatible with M68HC11 instruction set

ii. Interrupt stacking and programmer’s model identical to M68HC11

iii.Instruction queue

iv. Enhanced indexed addressing

– MEBI (Multiplexed External Bus Interface)

– MMC (Module Mapping Control)

– INT (Interrupt control)

– BKP (Breakpoints)

– BDM (Background Debug Mode)

• CRG (low current Colpitts or Pierce oscillator, PLL, reset, clocks, COP watchdog, real time

interrupt, clock monitor)

• 8-bit and 4-bit ports with interrupt functionality

– Digital filtering

– Programmable rising or falling edge trigger

• Memory

– 64K Flash EEPROM

– 1K byte EEPROM

– 4K byte RAM

• Two 8-channel Analog-to-Digital Converters

– 10-bit resolution

– External conversion trigger capability

• 1M bit per second, CAN 2.0 A, B software compatible module

– Five receive and three transmit buffers

– Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit or 8 x 8 bit

– Four separate interrupt channels for Rx, Tx, error and wake-up

– Low-pass filter wake-up function

– Loop-back for self test operation

• Enhanced Capture Timer

– 16-bit main counter with 7-bit prescaler

– 8 programmable input capture or output compare channels

– Four 8-bit or two 16-bit pulse accumulators

• 8 PWM channels

– Programmable period and duty cycle

– 8-bit 8-channel or 16-bit 4-channel

– Separate control for each pulse width and duty cycle

– Center-aligned or left-aligned outputs

– Programmable clock select logic with a wide range of frequencies

– Fast emergency shutdown input

– Usable as interrupt inputs

• Serial interfaces

– Two asynchronous Serial Communications Interfaces (SCI)

– Synchronous Serial Peripheral Interface (SPI)

• Byte Data Link Controller (BDLC)

– SAE J1850 Class B Data Communications Network Interface Compatible and ISO Compatible

for Low-Speed (<125 Kbps) Serial Data Communications in Automotive Applications

• Inter-IC Bus (IIC)

– Compatible with I2C Bus standard

– Multi-master operation

– Software programmable for one of 256 different serial clock frequencies

• 112-Pin LQFP or 80 QFP package

– I/O lines with 5V input and drive capability

– 5V A/D converter inputs

– Operation at 50MHz equivalent to 25MHz Bus Speed

– Development support

– Single-wire background debug™ mode (BDM)

– On-chip hardware breakpoints

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