NXP USA Inc.

HCS12X HCS12X Microcontroller IC 16-Bit 80MHz 512KB (512K x 8) FLASH 144-LQFP (20x20)

Introduction

The MC9S12XD family will retain the low cost, power consumption, EMC and code-size efficiency

advantages currently enjoyed by users of Freescale's existing 16-Bit MC9S12 MCU Family.

Based around an enhanced S12 core, the MC9S12XD family will deliver 2 to 5 times the performance of

a 25-MHz S12 whilst retaining a high degree of pin and code compatibility with the S12.

The MC9S12XD family introduces the performance boosting XGATE module. Using enhanced DMA

functionality, this parallel processing module offloads the CPU by providing high-speed data processing

and transfer between peripheral modules, RAM, Flash EEPROM and I/O ports. Providing up to 80 MIPS

of performance additional to the CPU, the XGATE can access all peripherals, Flash EEPROM and the

RAM block.

The MC9S12XD family is composed of standard on-chip peripherals including up to 512 Kbytes of Flash

EEPROM, 32 Kbytes of RAM, 4 Kbytes of EEPROM, six asynchronous serial communications interfaces

(SCI), three serial peripheral interfaces (SPI), an 8-channel IC/OC enhanced capture timer, an 8-channel,

10-bit analog-to-digital converter, a 16-channel, 10-bit analog-to-digital converter, an 8-channel

pulse-width modulator (PWM), five CAN 2.0 A, B software compatible modules (MSCAN12), two

inter-IC bus blocks, and a periodic interrupt timer. The MC9S12XD family has full 16-bit data paths

throughout.

The non-multiplexed expanded bus interface available on the 144-pin versions allows an easy interface to

external memories

The inclusion of a PLL circuit allows power consumption and performance to be adjusted to suit

operational requirements. System power consumption can be further improved with the new “fast exit from

stop mode” feature.

In addition to the I/O ports available in each module, up to 25 further I/O ports are available with interrupt

capability allowing wake-up from stop or wait mode.

Family members in 144-pin LQFP will be available with external bus interface and parts in 112-pin LQFP

or 80-pin QFP package without external bus interface. See Appendix E Derivative Differencesfor package

options.

 MC9S12XD/B/A Family Features

• HCS12X Core

— 16-bit HCS12X CPU

– Upward compatible with MC9S12 instruction set

– Interrupt stacking and programmer’s model identical to MC9S12

– Instruction queue

– Enhanced indexed addressing

– Enhanced instruction set

— EBI (external bus interface)

— MMC (module mapping control)

— INT (interrupt controller)

— DBG (debug module to monitor HCS12X CPU and XGATE bus activity)

— BDM (background debug mode)

• XGATE (peripheral coprocessor)

— Parallel processing module off loads the CPU by providing high-speed data processing and

transfer

— Data transfer between Flash EEPROM, RAM, peripheral modules, and I/O ports

• PIT (periodic interrupt timer)

— Four timers with independent time-out periods

— Time-out periods selectable between 1 and 224 bus clock cycles

• CRG (clock and reset generator)

— Low noise/low power Pierce oscillator

— PLL

— COP watchdog

— Real time interrupt

— Clock monitor

— Fast wake-up from stop mode

• Port H & Port J with interrupt functionality

— Digital filtering

— Programmable rising or falling edge trigger

• Memory

— 512, 256 and 128-Kbyte Flash EEPROM

— 4 and 2-Kbyte EEPROM

— 32, 16 and 12-Kbyte RAM

• One 16-channel and one 8-channel ADC (analog-to-digital converter)

— 10-bit resolution

— External and internal conversion trigger capabilityFiveFourTwo 1M bit per second,

CAN 2.0 A, B software compatible modules

— Five receive and three transmit buffers

— Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit, or 8 x 8 bit

— Four separate interrupt channels for Rx, Tx, error, and wake-up

— Low-pass filter wake-up function

— Loop-back for self-test operation

• ECT (enhanced capture timer)

— 16-bit main counter with 7-bit prescaler

— 8 programmable input capture or output compare channels

— Four 8-bit or two 16-bit pulse accumulators

• 8 PWM (pulse-width modulator) channels

— Programmable period and duty cycle

— 8-bit 8-channel or 16-bit 4-channel

— Separate control for each pulse width and duty cycle

— Center-aligned or left-aligned outputs

— Programmable clock select logic with a wide range of frequencies

— Fast emergency shutdown input

• Serial interfaces

— SixFourTwo asynchronous serial communication interfaces (SCI) with additional LIN support

and selectable IrDA 1.4 return-to-zero-inverted (RZI) format with programmable pulse width

— ThreeTwo Synchronous Serial Peripheral Interfaces (SPI)

• TwoOne IIC (Inter-IC bus) Modules

— Compatible with IIC bus standard

— Multi-master operation

— Software programmable for one of 256 different serial clock frequencies

• On-Chip Voltage Regulator

— Two parallel, linear voltage regulators with bandgap reference

— Low-voltage detect (LVD) with low-voltage interrupt (LVI)

— Power-on reset (POR) circuit

— 3.3-V–5.5-V operation

— Low-voltage reset (LVR)

— Ultra low-power wake-up timer

• 144-pin LQFP, 112-pin LQFP, and 80-pin QFP packages

— I/O lines with 5-V input and drive capability

— Input threshold on external bus interface inputs switchable for 3.3-V or 5-V operation

— 5-V A/D converter inputs

— Operation at 80 MHz equivalent to 40-MHz bus speed

• Development support

— Single-wire background debug™ mode (BDM)

— Four on-chip hardware breakpoints

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