A Comprehensive Guide To A3P250L-1PQG208 ProASIC3L Field Programmable Gate Array (FPGA) IC 151 36864 208-BFQFP

ProASIC3L Field Programmable Gate Array (FPGA) IC 151 36864 208-BFQFP

Clock Frequency Synthesis

Deriving clocks of various frequencies from a single reference clock is known as frequency synthesis.The PLL has an input

frequency range from 1.5 to 350 MHz. This frequency is automatically divideddown to a range between 1.5 MHz and

5.5 MHz by input dividers (not shown in Figure 4-19 on page 100)between PLL macro inputs and PLL phase detector

inputs. The VCO output is capable of an outputrange from 24 to 350 MHz. With dividers before the input to the PLL core

and following the VCO outputs,the VCO output frequency can be divided to provide the final frequency range from 0.75

to 350 MHz.Using SmartGen, the dividers are automatically set to achieve the closest possible matches to thespecified

output frequencies.

Users should be cautious when selecting the desired PLL input and output frequencies and the I/O bufferstandard used

to connect to the PLL input and output clocks. Depending on the I/O standards used forthe PLL input and output clocks,

the I/O frequencies have different maximum limits. Refer to the familydatasheets for specifications of maximum I/O

frequencies for supported I/O standards. Desired PLL inputor output frequencies will not be achieved if the selected

frequencies are higher than the maximum I/Ofrequencies allowed by the selected I/O standards. Users should be careful

when selecting the I/Ostandards used for PLL input and output clocks. Performing post-layout simulation can help detect

thistype of error, which will be identified with pulse width violation errors. Users are strongly encouraged toperform

post-layout simulation to ensure the I/O standard used can provide the desired PLL input oroutput frequencies. Users can

also choose to cascade PLLs together to achieve the high frequenciesneeded for their applications. Details of cascading

PLLs are discussed in the "Cascading CCCs" sectionon page 125.

In SmartGen, the actual generated frequency (under typical operating conditions) will be displayedbeside the requested

output frequency value. This provides the ability to determine the exact frequencythat can be generated by SmartGen, in

real time. The log file generated by SmartGen is a useful tool indetermining how closely the requested clock frequencies

match the user specifications. For example,assume a user specifies 101 MHz as one of the secondary output frequencies.

If the best outputfrequency that could be achieved were 100 MHz, the log file generated by SmartGen would indicate

theactual generated frequency

How to choose FPGA for your project?

PDF