A Comprehensive Guide To DSP56F801FA60E Microcontroller IC 16-Bit 60MHz 16KB (8K x 16) FLASH 48-LQFP (7x7)

56800 56F8xx Microcontroller IC 16-Bit 60MHz 16KB (8K x 16) FLASH 48-LQFP (7x7)

56F801 Description

The 56F801 is a member of the 56800 core-based family of processors. It combines, on a single chip, the

processing power of a DSP and the functionality of a microcontroller with a flexible set of peripherals to

create an extremely cost-effective solution. Because of its low cost, configuration flexibility, and

compact program code, the 56F801 is well-suited for many applications. The 56F801 includes many

peripherals that are especially useful for applications such as motion control, smart appliances, steppers,

encoders, tachometers, limit switches, power supply and control, automotive control, engine

management, noise suppression, remote utility metering, and industrial control for power, lighting, and

automation.

The 56800 core is based on a Harvard-style architecture consisting of three execution units operating in

parallel, allowing as many as six operations per instruction cycle. The microprocessor-style programming

model and optimized instruction set allow straightforward generation of efficient, compact code for both

DSP and MCU applications. The instruction set is also highly efficient for C compilers to enable rapid

development of optimized control applications.

The 56F801 supports program execution from either internal or external memories. Two data operands can

be accessed from the on-chip Data RAM per instruction cycle. The 56F801 also provides one external

dedicated interrupt lines and up to 11 General Purpose Input/Output (GPIO) lines, depending on peripheral

configuration.

The 56F801 controller includes 8K words (16-bit) of Program Flash and 2K words of Data Flash (each

programmable through the JTAG port) with 1K words of both Program and Data RAM. A total of 2K

words of Boot Flash is incorporated for easy customer-inclusion of field-programmable software routines

that can be used to program the main Program and Data Flash memory areas. Both Program and Data Flash

memories can be independently bulk erased or erased in page sizes of 256 words. The Boot Flash memory

can also be either bulk or page erased.

A key application-specific feature of the 56F801 is the inclusion of a Pulse Width Modulator (PWM)

module. This modules incorporates six complementary, individually programmable PWM signal outputs

to enhance motor control functionality. Complementary operation permits programmable dead-time

insertion, and separate top and bottom output polarity control. The up-counter value is programmable to

support a continuously variable PWM frequency. Both edge- and center-aligned synchronous pulse width

control (0% to 100% modulation) are supported. The device is capable of controlling most motor types:

ACIM (AC Induction Motors), both BDC and BLDC (Brush and Brushless DC motors), SRM and VRM

(Switched and Variable Reluctance Motors), and stepper motors. The PWMs incorporate fault protection

and cycle-by-cycle current limiting with sufficient output drive capability to directly drive standard

opto-isolators. A “smoke-inhibit”, write-once protection feature for key parameters is also included. The

PWM is double-buffered and includes interrupt control to permit integral reload rates to be programmable

from 1 to 16. The PWM modules provide a reference output to synchronize the Analog-to-Digital

Converters.

The 56F801 incorporates an 8 input, 12-bit Analog-to-Digital Converter (ADC). A full set of standard

programmable peripherals is provided that include a Serial Communications Interface (SCI), a Serial

Peripheral Interface (SPI), and two Quad Timers. Any of these interfaces can be used as General-Purpose

Input/Outputs (GPIO) if that function is not required. An on-chip relaxation oscillator provides flexibility

in the choice of either on-chip or externally supplied frequency reference for chip timing operations.

Application code is used to select which source is to be used.

56F801 Features

Digital Signal Processing Core

• Efficient 16-bit 56800 family controller engine with dual Harvard architecture

• As many as 40 Million Instructions Per Second (MIPS) at 80MHz core frequency

• Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC)

• Two 36-bit accumulators including extension bits

• 16-bit bidirectional barrel shifter

• Parallel instruction set with unique processor addressing modes

• Hardware DO and REP loops

• Three internal address buses and one external address bus

• Four internal data buses and one external data bus

• Instruction set supports both DSP and controller functions

• Controller style addressing modes and instructions for compact code

• Efficient C compiler and local variable support

• Software subroutine and interrupt stack with depth limited only by memory

• JTAG/OnCE debug programming interface

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