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* Programmable Logic Device (PLD) IC Macrocells
General Description
The TIBPAL22VP10’is equivalent to the TIBPAL22V10A but offers additional flexibility in the output structure. The improved
output macrocell uses the registered outputs as inputs when in a high-impedance condition. This provides two additional output
configurations for a total of six possible macrocell configurations all of which are shown in Figure 1.
These devices contain up to 22 inputs and 10 outputs. They incorporate the unique capability of defining and programming the
architecture of each output on an individual basis. Outputs may be registered or nonregistered and inverting or noninverting. In
addition, the data may be fed back into the array from either the register or the I/O port. The ten potential outputs are enabled
through the use of individual product terms.
Further advantages can be seen in the introduction of variable product term distribution. This technique allocates from 8 to 16
logical product terms to each output for an average of 12 product terms per output. This variable allocation of terms allows far
more complex functions to be implemented than in previously available devices.
Circuit design is enhanced by the addition of a synchronous set and an asynchronous reset product term. These functions are
common to all registers. When the synchronous set product term is a logic 1, the output registers are loaded with a logic 1 on
the next low-to-high clock transition. When the asynchronous reset product term is a logic 1, the output registers are loaded
with a logic 0. The output logic level after set or reset depends on the polarity selected during programming. Output registers
can be preloaded to any desired state during testing. Preloading permits full logical verification during product testing.
With features such as programmable output logic macrocells and variable product term distribution, the TIBPAL22VP10' offers
quick design and development of custom LSI functions with complexities of 500 to 800 equivalent gates. Since each of the ten
output pins may be individually configured as inputs on either a temporary or permanent basis, functions requiring up to 21
inputs and a single output or down to 12 inputs and 10 outputs are possible.
A power-up clear function is supplied that forces all registered outputs to a predetermined state after power is applied to the
device. Registered outputs selected as active-low power-up with their outputs high.Registered outputs selected as active-high
power-up with their outputs low.
A single security fuse is provided on each device to discourage unauthorized copying of fuse patterns. Once blown, the
verification circuitry is disabled and all other fuses will appear to be open.
The TIBPAL22V10-20C is characterized for operation from 0℃ to 75°C. The TIBPAL22V10-25M is characterized for operation over
the full military temperature range of -55℃ to 125℃.
Features
Functionally Equivalent to the TIBPAL22V10/10A,with Additional Feedback Paths in the Output Logic Macrocell
Choice of Operating Speeds:
TIBPAL22VP10-20C...20 ns Max
TIBPAL22VP10-25M...25 ns Max
Variable Product Term Distribution Allows More Complex Functions to Be Implemented
Each Output Is User Programmable for Registered or Combinational Operation, Polarity, and Output Enable Control
TTL-Level Preload for lmproved Testability
Extra Terms Provide Logical Synchronous Set and Asynchronous Reset Capability
Fast Programming,High Programming Yield, and Unsurpassed Reliability Ensured Using Ti-W Fuses
AC and DC Testing Done at the Factory Utilizing Special Designed-In Test Features
Dependable Texas Instruments Quality and Reliability
Package Options Include Plastic Dual-In-Line and Chip Carrier Packages
How to choose FPGA for your project?
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Shipment Date
2025/11/09 AM
Delivery Date
5-10 business days
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| Shipping: | $28.63 |
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