HCS12X HCS12X Microcontroller IC 16-Bit 40MHz 64KB (64K x 8) FLASH 64-LQFP (10x10)

Catalog  

• Product Introduction

  To provide the most up-to-date information, the document revision on the World Wide Web is the most

  current. A printed copy may be an earlier revision. To verify you have the latest information available,

  refer to freescale.com.

  This document contains information for the complete S12XS Family and thus includes a set of separate

  flash (FTMR) module sections to cover the whole family. A full list of family members and options is

  included in the appendices.

  This document contains information for all constituent modules, with the exception of the CPU. For CPU

  information please refer to CPU12XV1 in the CPU12/CPU12X Reference Manual.

• Specifications

  Features of the S12XS Family are listed here. Please see Table D-1 for memory options and Table D-2 for

  the peripheral features that are available on the different family members.

  • 16-bit CPU12X

  — Upward compatible with S12 instruction set with the exception of five Fuzzy instructions

  (MEM, WAV, WAVR, REV, REVW) which have been removed

  — Enhanced indexed addressing

  — Access to large data segments independent of PPAGE

  Device Overview S12XS Family

  S12XS Family Reference Manual, Rev. 1.13

  20 Freescale Semiconductor

  • INT (interrupt module)

  — Seven levels of nested interrupts

  — Flexible assignment of interrupt sources to each interrupt level.

  — External non-maskable high priority interrupt (XIRQ)

  — The following inputs can act as Wake-up Interrupts

  – IRQ and non-maskable XIRQ

  – CAN receive pins

  – SCI receive pins

  – Depending on the package option up to 20 pins on ports J, H and P configurable as rising or

  falling edge sensitive

  • MMC (module mapping control)

  • DBG (debug module)

  — Monitoring of CPU bus with tag-type or force-type breakpoint requests

  — 64 x 64-bit circular trace buffer captures change-of-flow or memory access information

  • BDM (background debug mode)

  • OSC_LCP (oscillator)

  — Low power loop control Pierce oscillator utilizing a 4MHz to 16MHz crystal

  — Good noise immunity

  — Full-swing Pierce option utilizing a 2MHz to 40MHz crystal

  — Transconductance sized for optimum start-up margin for typical crystals

  • IPLL (Internally filtered, frequency modulated phase-locked-loop clock generation)

  — No external components required

  — Configurable option to spread spectrum for reduced EMC radiation (frequency modulation)

  • CRG (clock and reset generation)

  — COP watchdog

  — Real time interrupt

  — Clock monitor

  — Fast wake up from STOP in self clock mode

  • Memory Options

  — 64, 128 and 256 Kbyte Flash

  — Flash General Features

  – 64 data bits plus 8 syndrome ECC (Error Correction Code) bits allow single bit failure

  correction and double fault detection

  – Erase sector size 1024 bytes

  – Automated program and erase algorithm

  – Protection scheme to prevent accidental program or erase

  – Security option to prevent unauthorized access

  – Sense-amp margin level setting for reads

  — 4 and 8 Kbyte Data Flash space

• Datasheet PDF

https://rocelec.widen.net/view/pdf/xlz4a1mesi/FSCLS07362-1.pdf?t.download=true&u=5oefqw

Application Q＆A

Q:Mc9S12xs128 Is the microcontroller only one timer can use?can run both timers at once？

Reference answer：Two cars can be run together at the same time。

Pin Assignments 64-pin LQFP Package

How read the label of the NXP chip？

What is the naming rules of NXP microcontrollers?

See the video for the answer--

PDF

Refer to alternative Part：

MC9S12XS128CAE

MC9S12XS256CAE