Intel

Cyclone® Field Programmable Gate Array (FPGA) IC 185 239616 12060 256-BGA

Introduction

The Cyclone® field programmable gate array family is based on a 1.5-V,

0.13-μm, all-layer copper SRAM process, with densities up to

20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like

phase-locked loops (PLLs) for clocking and a dedicated double data rate

(DDR) interface to meet DDR SDRAM and fast cycle RAM (FCRAM)

memory requirements, Cyclone devices are a cost-effective solution for

data-path applications. Cyclone devices support various I/O standards,

including LVDS at data rates up to 640 megabits per second (Mbps), and

66- and 33-MHz, 64- and 32-bit peripheral component interconnect (PCI),

for interfacing with and supporting ASSP and ASIC devices. Altera also

offers new low-cost serial configuration devices to configure Cyclone

devices.

Features

The Cyclone device family offers the following features:

■ 2,910 to 20,060 LEs, see Table 1–1

■ Up to 294,912 RAM bits (36,864 bytes)

■ Supports configuration through low-cost serial configuration device

■ Support for LVTTL, LVCMOS, SSTL-2, and SSTL-3 I/O standards

■ Support for 66- and 33-MHz, 64- and 32-bit PCI standard

■ High-speed (640 Mbps) LVDS I/O support

■ Low-speed (311 Mbps) LVDS I/O support

■ 311-Mbps RSDS I/O support

■ Up to two PLLs per device provide clock multiplication and phase

shifting

■ Up to eight global clock lines with six clock resources available per

logic array block (LAB) row

■ Support for external memory, including DDR SDRAM (133 MHz),

FCRAM, and single data rate (SDR) SDRAM

■ Support for multiple intellectual property (IP) cores, including

Altera® MegaCore® functions and Altera Megafunctions Partners

Program (AMPPSM) megafunctions. 

Chip Altera Cyclone naming rules，Chinese chip Will replace it

PDF

Cyclone® Field Programmable Gate Array (FPGA) IC 233 294912 20060 324-BGA

Introduction

The Cyclone® field programmable gate array family is based on a 1.5-V,

0.13-μm, all-layer copper SRAM process, with densities up to

20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like

phase-locked loops (PLLs) for clocking and a dedicated double data rate

(DDR) interface to meet DDR SDRAM and fast cycle RAM (FCRAM)

memory requirements, Cyclone devices are a cost-effective solution for

data-path applications. Cyclone devices support various I/O standards,

including LVDS at data rates up to 640 megabits per second (Mbps), and

66- and 33-MHz, 64- and 32-bit peripheral component interconnect (PCI),

for interfacing with and supporting ASSP and ASIC devices. Altera also

offers new low-cost serial configuration devices to configure Cyclone

devices.

Features

The Cyclone device family offers the following features:

■ 2,910 to 20,060 LEs, see Table 1–1

■ Up to 294,912 RAM bits (36,864 bytes)

■ Supports configuration through low-cost serial configuration device

■ Support for LVTTL, LVCMOS, SSTL-2, and SSTL-3 I/O standards

■ Support for 66- and 33-MHz, 64- and 32-bit PCI standard

■ High-speed (640 Mbps) LVDS I/O support

■ Low-speed (311 Mbps) LVDS I/O support

■ 311-Mbps RSDS I/O support

■ Up to two PLLs per device provide clock multiplication and phase

shifting

■ Up to eight global clock lines with six clock resources available per

logic array block (LAB) row

■ Support for external memory, including DDR SDRAM (133 MHz),

FCRAM, and single data rate (SDR) SDRAM

■ Support for multiple intellectual property (IP) cores, including

Altera® MegaCore® functions and Altera Megafunctions Partners

Program (AMPPSM) megafunctions. 

Chip Altera Cyclone naming rules，Chinese chip Will replace it

PDF

Cyclone® Field Programmable Gate Array (FPGA) IC 98 92160 5980 144-LQFP

Introduction

The Cyclone® field programmable gate array family is based on a 1.5-V,

0.13-μm, all-layer copper SRAM process, with densities up to

20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like

phase-locked loops (PLLs) for clocking and a dedicated double data rate

(DDR) interface to meet DDR SDRAM and fast cycle RAM (FCRAM)

memory requirements, Cyclone devices are a cost-effective solution for

data-path applications. Cyclone devices support various I/O standards,

including LVDS at data rates up to 640 megabits per second (Mbps), and

66- and 33-MHz, 64- and 32-bit peripheral component interconnect (PCI),

for interfacing with and supporting ASSP and ASIC devices. Altera also

offers new low-cost serial configuration devices to configure Cyclone

devices.

Features

The Cyclone device family offers the following features:

■ 2,910 to 20,060 LEs, see Table 1–1

■ Up to 294,912 RAM bits (36,864 bytes)

■ Supports configuration through low-cost serial configuration device

■ Support for LVTTL, LVCMOS, SSTL-2, and SSTL-3 I/O standards

■ Support for 66- and 33-MHz, 64- and 32-bit PCI standard

■ High-speed (640 Mbps) LVDS I/O support

■ Low-speed (311 Mbps) LVDS I/O support

■ 311-Mbps RSDS I/O support

■ Up to two PLLs per device provide clock multiplication and phase

shifting

■ Up to eight global clock lines with six clock resources available per

logic array block (LAB) row

■ Support for external memory, including DDR SDRAM (133 MHz),

FCRAM, and single data rate (SDR) SDRAM

■ Support for multiple intellectual property (IP) cores, including

Altera® MegaCore® functions and Altera Megafunctions Partners

Program (AMPPSM) megafunctions. 

Chip Altera Cyclone naming rules，Chinese chip Will replace it

PDF

Cyclone® Field Programmable Gate Array (FPGA) IC 173 239616 12060 240-BFQFP

Introduction

The Cyclone® field programmable gate array family is based on a 1.5-V,

0.13-μm, all-layer copper SRAM process, with densities up to

20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like

phase-locked loops (PLLs) for clocking and a dedicated double data rate

(DDR) interface to meet DDR SDRAM and fast cycle RAM (FCRAM)

memory requirements, Cyclone devices are a cost-effective solution for

data-path applications. Cyclone devices support various I/O standards,

including LVDS at data rates up to 640 megabits per second (Mbps), and

66- and 33-MHz, 64- and 32-bit peripheral component interconnect (PCI),

for interfacing with and supporting ASSP and ASIC devices. Altera also

offers new low-cost serial configuration devices to configure Cyclone

devices.

Features

The Cyclone device family offers the following features:

■ 2,910 to 20,060 LEs, see Table 1–1

■ Up to 294,912 RAM bits (36,864 bytes)

■ Supports configuration through low-cost serial configuration device

■ Support for LVTTL, LVCMOS, SSTL-2, and SSTL-3 I/O standards

■ Support for 66- and 33-MHz, 64- and 32-bit PCI standard

■ High-speed (640 Mbps) LVDS I/O support

■ Low-speed (311 Mbps) LVDS I/O support

■ 311-Mbps RSDS I/O support

■ Up to two PLLs per device provide clock multiplication and phase

shifting

■ Up to eight global clock lines with six clock resources available per

logic array block (LAB) row

■ Support for external memory, including DDR SDRAM (133 MHz),

FCRAM, and single data rate (SDR) SDRAM

■ Support for multiple intellectual property (IP) cores, including

Altera® MegaCore® functions and Altera Megafunctions Partners

Program (AMPPSM) megafunctions. 

Chip Altera Cyclone naming rules，Chinese chip Will replace it

PDF

Cyclone® III Field Programmable Gate Array (FPGA) IC 215 608256 24624 324-BGA

Cyclone III Device Family Overview

Cyclone® III device family offers a unique combination of high functionality, low

power and low cost. Based on Taiwan Semiconductor Manufacturing Company

(TSMC) low-power (LP) process technology, silicon optimizations and software

features to minimize power consumption, Cyclone III device family provides the ideal

solution for your high-volume, low-power, and cost-sensitive applications. To address

the unique design needs, Cyclone III device family offers the following two variants:

■ Cyclone III—lowest power, high functionality with the lowest cost

■ Cyclone III LS—lowest power FPGAs with security

With densities ranging from about 5,000 to 200,000 logic elements (LEs) and

0.5 Megabits (Mb) to 8 Mb of memory for less than ¼ watt of static power

consumption, Cyclone III device family makes it easier for you to meet your power

budget. Cyclone III LS devices are the first to implement a suite of security features at

the silicon, software, and intellectual property (IP) level on a low-power and

high-functionality FPGA platform. This suite of security features protects the IP from

tampering, reverse engineering and cloning. In addition, Cyclone III LS devices

support design separation which enables you to introduce redundancy in a single

chip to reduce size, weight, and power of your application.

Cyclone III Device Family Features

Cyclone III device family offers the following features:

Lowest Power FPGAs

■ Lowest power consumption with TSMC low-power process technology and

Altera® power-aware design flow

■ Low-power operation offers the following benefits:

■ Extended battery life for portable and handheld applications

■ Reduced or eliminated cooling system costs

■ Operation in thermally-challenged environments

■ Hot-socketing operation support

Design Security Feature

Cyclone III LS devices offer the following design security features:

■ Configuration security using advanced encryption standard (AES) with 256-bit

volatile key

■ Routing architecture optimized for design separation flow with the Quartus® II

software

■ Design separation flow achieves both physical and functional isolation

between design partitions

■ Ability to disable external JTAG port

■ Error Detection (ED) Cycle Indicator to core

■ Provides a pass or fail indicator at every ED cycle

■ Provides visibility over intentional or unintentional change of configuration

random access memory (CRAM) bits

■ Ability to perform zeroization to clear contents of the FPGA logic, CRAM,

embedded memory, and AES key

■ Internal oscillator enables system monitor and health check capabilities

Chip Altera Cyclone naming rules，Chinese chip Will replace it

PDF

Cyclone® 10 GX Field Programmable Gate Array (FPGA) IC 284 10907648 150000 780-BBGA, FCBGA

Summary of Intel Cyclone 10 GX Features

Technology

TSMC's 20-nm process technology

Packaging

• 1.0 mm ball-pitch FineLine BGA packaging

• 0.8 mm ball-pitch Ultra FineLine BGA packaging

• Multiple devices with identical package footprints for seamless migration between different FPGA densities

• RoHS6-compliance

High-performance FPGA fabric

• Enhanced 8-input ALM with four registers

• Improved multi-track routing architecture to reduce congestion and improve compilation time

• Hierarchical core clocking architecture

• Fine-grained partial reconfiguration

Internal memory blocks

• M20K—20-Kb memory blocks with hard error correction code (ECC), cascadable

• Memory logic array block (MLAB)—640-bit memory, cascadable

Embedded Hard IP blocks

Variable-precision DSP

• Native support for signal processing precision levels from 18 x 19 to 54 x 54, cascadable

• Native support for 27 x 27 multiplier mode

• 64-bit accumulator and cascade for systolic finite impulse responses (FIRs)

• Internal coefficient memory banks

• Preadder/subtractor for improved efficiency

• Additional pipeline register to increase performance and reduce power

• Supports floating point arithmetic:

   — Perform multiplication, addition, subtraction, multiply-add,

multiply-subtract, and complex multiplication.

   — Supports multiplication with accumulation capability, cascade

summation, and cascade subtraction capability.

   — Dynamic accumulator reset control.

   — Support direct vector dot and complex multiplication chaining multiply floating point DSP blocks.

Memory controller

DDR3, DDR3L, and LPDDR3

PCI Express®

PCI Express (PCIe®) Gen2 (x1, x2, or x4) and Gen1 (x1, x2, or x4) hard IP with complete protocol stack, endpoint, and root port.

Transceiver I/O

• PCS hard IPs that support:

   — 10 Gbps Ethernet (10GbE) (1)

   — PCIe PIPE interface

   — Interlaken

   — Gbps Ethernet (GbE)

   — 6G Common Public Radio Interface (CPRI) with deterministic latency support

   — Gigabit-capable passive optical network (GPON) with fast locktime support

• 12G Serial Digital Interface (SDI)

• 8B/10B, 64B/66B, 64B/67B encoders and decoders

• Custom mode support for proprietary protocols

Core clock networks

• Up to 300 MHz fabric clocking, depending on the application:

   — 467 MHz external memory interface clocking with 1,866 Mbps DDR3 interface

   — 300 MHz LVDS interface clocking with 1.434 Gbps LVDS interface

• Global, regional, and peripheral clock networks

• Clock networks that are not used can be gated to reduce dynamic power

Phase-locked loops(PLLs)

• High-resolution fractional synthesis PLLs:

   — Precision clock synthesis, clock delay compensation, and zero delay buffering (ZDB)

   — Support integer mode and fractional mode

   — Fractional mode support with third-order delta-sigma modulation

• Integer PLLs:

   — Adjacent to general purpose I/Os

   — Support external memory and LVDS interfaces

FPGA General-purpose I/Os (GPIOs)

• One 3 V I/O bank supporting up to 3.0 V I/O standards

• Up to 1.434 Gbps LVDS—every pair can be configured as receiver or transmitter

• On-chip termination (OCT)

• 1.2 V to 3.0 V single-ended LVTTL/LVCMOS interfaces using LVDS I/O or 3 V I/O banks

External Memory Interface

• Hard memory controller—DDR3, DDR3L, and LPDDR3 support

• DDR3 speeds up to 933 MHz/1,866 Mbps

Low-power serial transceivers

• Continuous operating range up to 12.5 Gbps

• Backplane support up to 6.6 Gbps

• Extended range down to 125 Mbps with oversampling

• ATX transmit PLLs with user-configurable fractional synthesis capability

• Transmitter pre-emphasis and de-emphasis

• Dynamic reconfiguration of individual transceiver channels

Configuration

• Tamper protection—comprehensive design protection to protect your valuable IP investments

• Enhanced 256-bit advanced encryption standard (AES) design security with authentication

• Configuration via protocol (CvP) using PCIe Gen1 or Gen2

• Dynamic reconfiguration of the transceivers and PLLs

• Fine-grained partial reconfiguration of the core fabric

• Active Serial ×4 Interface

Power management

• Programmable Power Technology

• Intel Quartus® Prime Pro Edition integrated power analysis tool

Software and tools

• Intel Quartus Prime Pro Edition design suite

• Transceiver toolkit

• Platform Designer (Standard) system integration tool

• DSP Builder advanced blockset

• OpenCL* support

Chip Altera Cyclone naming rules，Chinese chip Will replace it

PDF