ALTERA MAX Series Naming Rules,EPM2210F256C4N.

For more product unboxing videos, please click on the link

Relevant Content
EPM570T100I5N	IC CPLD 440MC 5.4NS 100TQFP	EP2C5T144I8N	Cyclone® II Field Programmable Gate Array (FPGA) IC 89 119808 4608 144-LQFP
EP4CE115F23I7N	Cyclone® IV E Field Programmable Gate Array (FPGA) IC 280 3981312 114480 484-BGA	5CGXFC5C6F27I7N	Cyclone® V GX Field Programmable Gate Array (FPGA) IC 336 5001216 77000 672-BGA
EP4CE22E22C8N	Cyclone® IV E Field Programmable Gate Array (FPGA) IC 79 608256 22320 144-LQFP Exposed Pad	EP4CE15F17I7N	Cyclone® IV E Field Programmable Gate Array (FPGA) IC 165 516096 15408 256-LBGA
EP2C5T144C8N	Cyclone® II Field Programmable Gate Array (FPGA) IC 89 119808 4608 144-LQFP	EN6347QI	DC DC CONVERTER 0.6-6.24V
EP4CE10E22I7N	Cyclone® IV E Field Programmable Gate Array (FPGA) IC 91 423936 10320 144-LQFP Exposed Pad	EP4CGX30CF23I7N	Cyclone® IV GX Field Programmable Gate Array (FPGA) IC 290 1105920 29440 484-BGA
5M570ZT100I5N	IC CPLD 440MC 9NS 100TQFP	5M40ZE64C5N	IC CPLD 32MC 7.5NS 64EQFP
EPCQ64ASI16N	IC CONFIG DEVICE 64MBIT 16SOIC	EPM240T100C5N	IC CPLD 192MC 4.7NS 100TQFP

Cyclone® Field Programmable Gate Array (FPGA) IC 185 239616 12060 256-BGA

Introduction

The Cyclone® field programmable gate array family is based on a 1.5-V,

0.13-μm, all-layer copper SRAM process, with densities up to

20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like

phase-locked loops (PLLs) for clocking and a dedicated double data rate

(DDR) interface to meet DDR SDRAM and fast cycle RAM (FCRAM)

memory requirements, Cyclone devices are a cost-effective solution for

data-path applications. Cyclone devices support various I/O standards,

including LVDS at data rates up to 640 megabits per second (Mbps), and

66- and 33-MHz, 64- and 32-bit peripheral component interconnect (PCI),

for interfacing with and supporting ASSP and ASIC devices. Altera also

offers new low-cost serial configuration devices to configure Cyclone

devices.

Features

The Cyclone device family offers the following features:

■ 2,910 to 20,060 LEs, see Table 1–1

■ Up to 294,912 RAM bits (36,864 bytes)

■ Supports configuration through low-cost serial configuration device

■ Support for LVTTL, LVCMOS, SSTL-2, and SSTL-3 I/O standards

■ Support for 66- and 33-MHz, 64- and 32-bit PCI standard

■ High-speed (640 Mbps) LVDS I/O support

■ Low-speed (311 Mbps) LVDS I/O support

■ 311-Mbps RSDS I/O support

■ Up to two PLLs per device provide clock multiplication and phase

shifting

■ Up to eight global clock lines with six clock resources available per

logic array block (LAB) row

■ Support for external memory, including DDR SDRAM (133 MHz),

FCRAM, and single data rate (SDR) SDRAM

■ Support for multiple intellectual property (IP) cores, including

Altera® MegaCore® functions and Altera Megafunctions Partners

Program (AMPPSM) megafunctions. 

Chip Altera Cyclone naming rules，Chinese chip Will replace it

PDF

Altera cyclone Naming rules,EP4CE40F29C8N

For more product unboxing videos, please click on the link

Relevant Content
EP4CE10E22C8N	Cyclone® IV E Field Programmable Gate Array (FPGA) IC 91 423936 10320 144-LQFP Exposed Pad	EPM570T100C5N	IC CPLD 440MC 5.4NS 100TQFP
EPM1270T144C5N	IC CPLD 980MC 6.2NS 144TQFP	EP4CE10F17C8N	Cyclone® IV E Field Programmable Gate Array (FPGA) IC 179 423936 10320 256-LBGA
EPCS4SI8N	IC CONFIG DEVICE 4MBIT 8SOIC	EPCQ4ASI8N	IC CONFIG DEVICE 4MBIT 8SOIC
EPCQ16ASI8N	IC CONFIG DEVICE 16MBIT 8SOIC	EP4CE15F23C8N	Cyclone® IV E Field Programmable Gate Array (FPGA) IC 343 516096 15408 484-BGA
EPCQ128ASI16N	IC CONFIG DEVICE 128MBIT 16SOIC	EP4CE6F17C8N	Cyclone® IV E Field Programmable Gate Array (FPGA) IC 179 276480 6272 256-LBGA
EPM1270F256I5N	IC CPLD 980MC 6.2NS 256FBGA	EP4CE22F17C8N	Cyclone® IV E Field Programmable Gate Array (FPGA) IC 153 608256 22320 256-LBGA
EP4CE6E22I7N	Cyclone® IV E Field Programmable Gate Array (FPGA) IC 91 276480 6272 144-LQFP Exposed Pad	EPM570T144C5N	IC CPLD 440MC 5.4NS 144TQFP

Cyclone® Field Programmable Gate Array (FPGA) IC 233 294912 20060 324-BGA

Introduction

The Cyclone® field programmable gate array family is based on a 1.5-V,

0.13-μm, all-layer copper SRAM process, with densities up to

20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like

phase-locked loops (PLLs) for clocking and a dedicated double data rate

(DDR) interface to meet DDR SDRAM and fast cycle RAM (FCRAM)

memory requirements, Cyclone devices are a cost-effective solution for

data-path applications. Cyclone devices support various I/O standards,

including LVDS at data rates up to 640 megabits per second (Mbps), and

66- and 33-MHz, 64- and 32-bit peripheral component interconnect (PCI),

for interfacing with and supporting ASSP and ASIC devices. Altera also

offers new low-cost serial configuration devices to configure Cyclone

devices.

Features

The Cyclone device family offers the following features:

■ 2,910 to 20,060 LEs, see Table 1–1

■ Up to 294,912 RAM bits (36,864 bytes)

■ Supports configuration through low-cost serial configuration device

■ Support for LVTTL, LVCMOS, SSTL-2, and SSTL-3 I/O standards

■ Support for 66- and 33-MHz, 64- and 32-bit PCI standard

■ High-speed (640 Mbps) LVDS I/O support

■ Low-speed (311 Mbps) LVDS I/O support

■ 311-Mbps RSDS I/O support

■ Up to two PLLs per device provide clock multiplication and phase

shifting

■ Up to eight global clock lines with six clock resources available per

logic array block (LAB) row

■ Support for external memory, including DDR SDRAM (133 MHz),

FCRAM, and single data rate (SDR) SDRAM

■ Support for multiple intellectual property (IP) cores, including

Altera® MegaCore® functions and Altera Megafunctions Partners

Program (AMPPSM) megafunctions. 

Chip Altera Cyclone naming rules，Chinese chip Will replace it

PDF

Cyclone® Field Programmable Gate Array (FPGA) IC 98 92160 5980 144-LQFP

Introduction

The Cyclone® field programmable gate array family is based on a 1.5-V,

0.13-μm, all-layer copper SRAM process, with densities up to

20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like

phase-locked loops (PLLs) for clocking and a dedicated double data rate

(DDR) interface to meet DDR SDRAM and fast cycle RAM (FCRAM)

memory requirements, Cyclone devices are a cost-effective solution for

data-path applications. Cyclone devices support various I/O standards,

including LVDS at data rates up to 640 megabits per second (Mbps), and

66- and 33-MHz, 64- and 32-bit peripheral component interconnect (PCI),

for interfacing with and supporting ASSP and ASIC devices. Altera also

offers new low-cost serial configuration devices to configure Cyclone

devices.

Features

The Cyclone device family offers the following features:

■ 2,910 to 20,060 LEs, see Table 1–1

■ Up to 294,912 RAM bits (36,864 bytes)

■ Supports configuration through low-cost serial configuration device

■ Support for LVTTL, LVCMOS, SSTL-2, and SSTL-3 I/O standards

■ Support for 66- and 33-MHz, 64- and 32-bit PCI standard

■ High-speed (640 Mbps) LVDS I/O support

■ Low-speed (311 Mbps) LVDS I/O support

■ 311-Mbps RSDS I/O support

■ Up to two PLLs per device provide clock multiplication and phase

shifting

■ Up to eight global clock lines with six clock resources available per

logic array block (LAB) row

■ Support for external memory, including DDR SDRAM (133 MHz),

FCRAM, and single data rate (SDR) SDRAM

■ Support for multiple intellectual property (IP) cores, including

Altera® MegaCore® functions and Altera Megafunctions Partners

Program (AMPPSM) megafunctions. 

Chip Altera Cyclone naming rules，Chinese chip Will replace it

PDF

Cyclone® Field Programmable Gate Array (FPGA) IC 173 239616 12060 240-BFQFP

Introduction

The Cyclone® field programmable gate array family is based on a 1.5-V,

0.13-μm, all-layer copper SRAM process, with densities up to

20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like

phase-locked loops (PLLs) for clocking and a dedicated double data rate

(DDR) interface to meet DDR SDRAM and fast cycle RAM (FCRAM)

memory requirements, Cyclone devices are a cost-effective solution for

data-path applications. Cyclone devices support various I/O standards,

including LVDS at data rates up to 640 megabits per second (Mbps), and

66- and 33-MHz, 64- and 32-bit peripheral component interconnect (PCI),

for interfacing with and supporting ASSP and ASIC devices. Altera also

offers new low-cost serial configuration devices to configure Cyclone

devices.

Features

The Cyclone device family offers the following features:

■ 2,910 to 20,060 LEs, see Table 1–1

■ Up to 294,912 RAM bits (36,864 bytes)

■ Supports configuration through low-cost serial configuration device

■ Support for LVTTL, LVCMOS, SSTL-2, and SSTL-3 I/O standards

■ Support for 66- and 33-MHz, 64- and 32-bit PCI standard

■ High-speed (640 Mbps) LVDS I/O support

■ Low-speed (311 Mbps) LVDS I/O support

■ 311-Mbps RSDS I/O support

■ Up to two PLLs per device provide clock multiplication and phase

shifting

■ Up to eight global clock lines with six clock resources available per

logic array block (LAB) row

■ Support for external memory, including DDR SDRAM (133 MHz),

FCRAM, and single data rate (SDR) SDRAM

■ Support for multiple intellectual property (IP) cores, including

Altera® MegaCore® functions and Altera Megafunctions Partners

Program (AMPPSM) megafunctions. 

Chip Altera Cyclone naming rules，Chinese chip Will replace it

PDF