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    Rfq
    5SGXEA7K2F40I3G
    Stratix® V GX Field Programmable Gate Array (FPGA) IC 696 51200000 622000 1517-BBGA, FCBGA
    1060
    1517-BBGA, FCBGA
    AGIB019R18A2I3V
    System On Chip (SOC) IC *
    2454
    EP2AGX95EF29C4N
    Arria II GX Field Programmable Gate Array (FPGA) IC 372 6839296 89178 780-BBGA, FCBGA
    8240
    780-BBGA, FCBGA
    5ASXFB3H4F40I5N
    Dual ARM® Cortex®-A9 MPCore™ with CoreSight™ System On Chip (SOC) IC Arria V SX FPGA - 350K Logic Elements 800MHz 1517-FBGA, FC (40x40)
    9836
    1517-BBGA, FCBGA
    5SGXEABN2F45I2G
    Stratix® V GX Field Programmable Gate Array (FPGA) IC 840 53248000 952000 1932-BBGA, FCBGA
    9265
    1932-BBGA, FCBGA
    AGFB019R31C2E2VB
    * Field Programmable Gate Array (FPGA) IC
    1673
    AGFB019R31C2E2VB
    EP2AGX190EF29C4N
    Arria II GX Field Programmable Gate Array (FPGA) IC 372 10177536 181165 780-BBGA, FCBGA
    4171
    780-BBGA, FCBGA
    5ASXMB3G4F40C4N
    Dual ARM® Cortex®-A9 MPCore™ with CoreSight™ System On Chip (SOC) IC Arria V SX FPGA - 350K Logic Elements 925MHz 1517-FBGA, FC (40x40)
    1307
    1517-BBGA, FCBGA
    5SEEBF45I3G
    Stratix® V E Field Programmable Gate Array (FPGA) IC 840 53248000 952000 1932-BBGA, FCBGA
    5808
    1932-BBGA, FCBGA
    A Comprehensive Guide to EP1C12F324C6 Cyclone® Field Programmable Gate Array (FPGA) IC

    Cyclone® Field Programmable Gate Array (FPGA) IC 249 239616 12060 324-BGA


    Introduction

    The Cyclone® field programmable gate array family is based on a 1.5-V,

    0.13-μm, all-layer copper SRAM process, with densities up to

    20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like

    phase-locked loops (PLLs) for clocking and a dedicated double data rate

    (DDR) interface to meet DDR SDRAM and fast cycle RAM (FCRAM)

    memory requirements, Cyclone devices are a cost-effective solution for

    data-path applications. Cyclone devices support various I/O standards,

    including LVDS at data rates up to 640 megabits per second (Mbps), and

    66- and 33-MHz, 64- and 32-bit peripheral component interconnect (PCI),

    for interfacing with and supporting ASSP and ASIC devices. Altera also

    offers new low-cost serial configuration devices to configure Cyclone

    devices.


    Features

    The Cyclone device family offers the following features:

    ■ 2,910 to 20,060 LEs, see Table 1–1

    ■ Up to 294,912 RAM bits (36,864 bytes)

    ■ Supports configuration through low-cost serial configuration device

    ■ Support for LVTTL, LVCMOS, SSTL-2, and SSTL-3 I/O standards

    ■ Support for 66- and 33-MHz, 64- and 32-bit PCI standard

    ■ High-speed (640 Mbps) LVDS I/O support

    ■ Low-speed (311 Mbps) LVDS I/O support

    ■ 311-Mbps RSDS I/O support

    ■ Up to two PLLs per device provide clock multiplication and phase

    shifting

    ■ Up to eight global clock lines with six clock resources available per

    logic array block (LAB) row

    ■ Support for external memory, including DDR SDRAM (133 MHz),

    FCRAM, and single data rate (SDR) SDRAM

    ■ Support for multiple intellectual property (IP) cores, including

    Altera® MegaCore® functions and Altera Megafunctions Partners

    Program (AMPPSM) megafunctions. 


    Chip Altera Cyclone naming rules,Chinese chip Will replace it






    PDF

    1485
    324-BGA
    EP2AGX45CU17C4
    Arria II GX Field Programmable Gate Array (FPGA) IC 156 3517440 42959 358-LFBGA, FCBGA
    4265
    358-LFBGA, FCBGA
    EP20K60ETC144-1X
    APEX-20KE® Field Programmable Gate Array (FPGA) IC 92 32768 2560 144-LQFP
    7318
    144-LQFP
    5SGSED8K2F40C2LG
    Stratix® V GS Field Programmable Gate Array (FPGA) IC 696 51200000 695000 1517-BBGA, FCBGA
    6780
    1517-BBGA, FCBGA
    A Comprehensive Guide to EP1C3T144C6 Cyclone® Field Programmable Gate Array (FPGA) IC

    Cyclone® Field Programmable Gate Array (FPGA) IC 104 59904 2910 144-LQFP


    Introduction

    The Cyclone® field programmable gate array family is based on a 1.5-V,

    0.13-μm, all-layer copper SRAM process, with densities up to

    20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like

    phase-locked loops (PLLs) for clocking and a dedicated double data rate

    (DDR) interface to meet DDR SDRAM and fast cycle RAM (FCRAM)

    memory requirements, Cyclone devices are a cost-effective solution for

    data-path applications. Cyclone devices support various I/O standards,

    including LVDS at data rates up to 640 megabits per second (Mbps), and

    66- and 33-MHz, 64- and 32-bit peripheral component interconnect (PCI),

    for interfacing with and supporting ASSP and ASIC devices. Altera also

    offers new low-cost serial configuration devices to configure Cyclone

    devices.


    Features

    The Cyclone device family offers the following features:

    ■ 2,910 to 20,060 LEs, see Table 1–1

    ■ Up to 294,912 RAM bits (36,864 bytes)

    ■ Supports configuration through low-cost serial configuration device

    ■ Support for LVTTL, LVCMOS, SSTL-2, and SSTL-3 I/O standards

    ■ Support for 66- and 33-MHz, 64- and 32-bit PCI standard

    ■ High-speed (640 Mbps) LVDS I/O support

    ■ Low-speed (311 Mbps) LVDS I/O support

    ■ 311-Mbps RSDS I/O support

    ■ Up to two PLLs per device provide clock multiplication and phase

    shifting

    ■ Up to eight global clock lines with six clock resources available per

    logic array block (LAB) row

    ■ Support for external memory, including DDR SDRAM (133 MHz),

    FCRAM, and single data rate (SDR) SDRAM

    ■ Support for multiple intellectual property (IP) cores, including

    Altera® MegaCore® functions and Altera Megafunctions Partners

    Program (AMPPSM) megafunctions. 


    Chip Altera Cyclone naming rules,Chinese chip Will replace it






    PDF

    6083
    144-LQFP
    EP2AGX65DF25C6
    Arria II GX Field Programmable Gate Array (FPGA) IC 252 5371904 60214 572-BGA, FCBGA
    4637
    572-BGA, FCBGA
    10AS066H3F34I3SGES
    Dual ARM® Cortex®-A9 MPCore™ with CoreSight™ System On Chip (SOC) IC Arria 10 SX FPGA - 660K Logic Elements 1.5GHz 1152-FBGA, FC (35x35)
    5336
    1152-BBGA, FCBGA
    5SGXEA9N1F45C2G
    Stratix® V GX Field Programmable Gate Array (FPGA) IC 840 53248000 840000 1932-BBGA, FCBGA
    1914
    1932-BBGA, FCBGA
    A Comprehensive Guide to EP1C6Q240I7 Cyclone® Field Programmable Gate Array (FPGA) IC

    Cyclone® Field Programmable Gate Array (FPGA) IC 185 92160 5980 240-BFQFP


    Introduction

    The Cyclone® field programmable gate array family is based on a 1.5-V,

    0.13-μm, all-layer copper SRAM process, with densities up to

    20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like

    phase-locked loops (PLLs) for clocking and a dedicated double data rate

    (DDR) interface to meet DDR SDRAM and fast cycle RAM (FCRAM)

    memory requirements, Cyclone devices are a cost-effective solution for

    data-path applications. Cyclone devices support various I/O standards,

    including LVDS at data rates up to 640 megabits per second (Mbps), and

    66- and 33-MHz, 64- and 32-bit peripheral component interconnect (PCI),

    for interfacing with and supporting ASSP and ASIC devices. Altera also

    offers new low-cost serial configuration devices to configure Cyclone

    devices.


    Features

    The Cyclone device family offers the following features:

    ■ 2,910 to 20,060 LEs, see Table 1–1

    ■ Up to 294,912 RAM bits (36,864 bytes)

    ■ Supports configuration through low-cost serial configuration device

    ■ Support for LVTTL, LVCMOS, SSTL-2, and SSTL-3 I/O standards

    ■ Support for 66- and 33-MHz, 64- and 32-bit PCI standard

    ■ High-speed (640 Mbps) LVDS I/O support

    ■ Low-speed (311 Mbps) LVDS I/O support

    ■ 311-Mbps RSDS I/O support

    ■ Up to two PLLs per device provide clock multiplication and phase

    shifting

    ■ Up to eight global clock lines with six clock resources available per

    logic array block (LAB) row

    ■ Support for external memory, including DDR SDRAM (133 MHz),

    FCRAM, and single data rate (SDR) SDRAM

    ■ Support for multiple intellectual property (IP) cores, including

    Altera® MegaCore® functions and Altera Megafunctions Partners

    Program (AMPPSM) megafunctions. 


    Chip Altera Cyclone naming rules,Chinese chip Will replace it






    PDF

    4033
    240-BFQFP
    EP2AGX95EF29C5
    Arria II GX Field Programmable Gate Array (FPGA) IC 372 6839296 89178 780-BBGA, FCBGA
    8858
    780-BBGA, FCBGA
    10AX066K4F35I4SGES
    Arria 10 GX Field Programmable Gate Array (FPGA) IC 396 49610752 660000 1152-BBGA, FCBGA
    1678
    1152-BBGA, FCBGA
    5SGXEA5N2F45C3G
    Stratix® V GX Field Programmable Gate Array (FPGA) IC 840 46080000 490000 1932-BBGA, FCBGA
    7230
    1932-BBGA, FCBGA
    A Comprehensive Guide to EP1C3T100C7N Cyclone® Field Programmable Gate Array (FPGA) IC

    Cyclone® Field Programmable Gate Array (FPGA) IC 65 59904 2910 100-TQFP


    Introduction

    The Cyclone® field programmable gate array family is based on a 1.5-V,

    0.13-μm, all-layer copper SRAM process, with densities up to

    20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like

    phase-locked loops (PLLs) for clocking and a dedicated double data rate

    (DDR) interface to meet DDR SDRAM and fast cycle RAM (FCRAM)

    memory requirements, Cyclone devices are a cost-effective solution for

    data-path applications. Cyclone devices support various I/O standards,

    including LVDS at data rates up to 640 megabits per second (Mbps), and

    66- and 33-MHz, 64- and 32-bit peripheral component interconnect (PCI),

    for interfacing with and supporting ASSP and ASIC devices. Altera also

    offers new low-cost serial configuration devices to configure Cyclone

    devices.


    Features

    The Cyclone device family offers the following features:

    ■ 2,910 to 20,060 LEs, see Table 1–1

    ■ Up to 294,912 RAM bits (36,864 bytes)

    ■ Supports configuration through low-cost serial configuration device

    ■ Support for LVTTL, LVCMOS, SSTL-2, and SSTL-3 I/O standards

    ■ Support for 66- and 33-MHz, 64- and 32-bit PCI standard

    ■ High-speed (640 Mbps) LVDS I/O support

    ■ Low-speed (311 Mbps) LVDS I/O support

    ■ 311-Mbps RSDS I/O support

    ■ Up to two PLLs per device provide clock multiplication and phase

    shifting

    ■ Up to eight global clock lines with six clock resources available per

    logic array block (LAB) row

    ■ Support for external memory, including DDR SDRAM (133 MHz),

    FCRAM, and single data rate (SDR) SDRAM

    ■ Support for multiple intellectual property (IP) cores, including

    Altera® MegaCore® functions and Altera Megafunctions Partners

    Program (AMPPSM) megafunctions. 


    Chip Altera Cyclone naming rules,Chinese chip Will replace it






    PDF

    2634
    100-TQFP
    EP2AGX125EF29C4
    Arria II GX Field Programmable Gate Array (FPGA) IC 372 8315904 118143 780-BBGA, FCBGA
    2568
    780-BBGA, FCBGA
    EPCQ512ASI16N
    IC QUAD-SERIAL CONFIG DEVICE 512
    1553
    16-SOIC (0.295", 7.50mm Width)
    5SGSMD8N2F45I2LG
    Stratix® V GS Field Programmable Gate Array (FPGA) IC 840 51200000 695000 1932-BBGA, FCBGA
    6229
    1932-BBGA, FCBGA
    A Comprehensive Guide to 10CX085YF672I5G Cyclone® 10 GX Field Programmable Gate Array (FPGA) IC

    Cyclone® 10 GX Field Programmable Gate Array (FPGA) IC 216 5959680 85000 672-BGA


    Summary of Intel Cyclone 10 GX Features

    Technology

    TSMC's 20-nm process technology


    Packaging

    • 1.0 mm ball-pitch FineLine BGA packaging

    • 0.8 mm ball-pitch Ultra FineLine BGA packaging

    • Multiple devices with identical package footprints for seamless migration between different FPGA densities

    • RoHS6-compliance


    High-performance FPGA fabric

    • Enhanced 8-input ALM with four registers

    • Improved multi-track routing architecture to reduce congestion and improve compilation time

    • Hierarchical core clocking architecture

    • Fine-grained partial reconfiguration


    Internal memory blocks

    • M20K—20-Kb memory blocks with hard error correction code (ECC), cascadable

    • Memory logic array block (MLAB)—640-bit memory, cascadable


    Embedded Hard IP blocks

    Variable-precision DSP

    • Native support for signal processing precision levels from 18 x 19 to 54 x 54, cascadable

    • Native support for 27 x 27 multiplier mode

    • 64-bit accumulator and cascade for systolic finite impulse responses (FIRs)

    • Internal coefficient memory banks

    • Preadder/subtractor for improved efficiency

    • Additional pipeline register to increase performance and reduce power

    • Supports floating point arithmetic:

       — Perform multiplication, addition, subtraction, multiply-add,

    multiply-subtract, and complex multiplication.

       — Supports multiplication with accumulation capability, cascade

    summation, and cascade subtraction capability.

       — Dynamic accumulator reset control.

       — Support direct vector dot and complex multiplication chaining multiply floating point DSP blocks.


    Memory controller

    DDR3, DDR3L, and LPDDR3


    PCI Express®

    PCI Express (PCIe®) Gen2 (x1, x2, or x4) and Gen1 (x1, x2, or x4) hard IP with complete protocol stack, endpoint, and root port.


    Transceiver I/O

    • PCS hard IPs that support:

       — 10 Gbps Ethernet (10GbE) (1)

       — PCIe PIPE interface

       — Interlaken

       — Gbps Ethernet (GbE)

       — 6G Common Public Radio Interface (CPRI) with deterministic latency support

       — Gigabit-capable passive optical network (GPON) with fast locktime support

    • 12G Serial Digital Interface (SDI)

    • 8B/10B, 64B/66B, 64B/67B encoders and decoders

    • Custom mode support for proprietary protocols


    Core clock networks

    • Up to 300 MHz fabric clocking, depending on the application:

       — 467 MHz external memory interface clocking with 1,866 Mbps DDR3 interface

       — 300 MHz LVDS interface clocking with 1.434 Gbps LVDS interface

    • Global, regional, and peripheral clock networks

    • Clock networks that are not used can be gated to reduce dynamic power


    Phase-locked loops(PLLs)

    • High-resolution fractional synthesis PLLs:

       — Precision clock synthesis, clock delay compensation, and zero delay buffering (ZDB)

       — Support integer mode and fractional mode

       — Fractional mode support with third-order delta-sigma modulation

    • Integer PLLs:

       — Adjacent to general purpose I/Os

       — Support external memory and LVDS interfaces


    FPGA General-purpose I/Os (GPIOs)

    • One 3 V I/O bank supporting up to 3.0 V I/O standards

    • Up to 1.434 Gbps LVDS—every pair can be configured as receiver or transmitter

    • On-chip termination (OCT)

    • 1.2 V to 3.0 V single-ended LVTTL/LVCMOS interfaces using LVDS I/O or 3 V I/O banks


    External Memory Interface

    • Hard memory controller—DDR3, DDR3L, and LPDDR3 support

    • DDR3 speeds up to 933 MHz/1,866 Mbps


    Low-power serial transceivers

    • Continuous operating range up to 12.5 Gbps

    • Backplane support up to 6.6 Gbps

    • Extended range down to 125 Mbps with oversampling

    • ATX transmit PLLs with user-configurable fractional synthesis capability

    • Transmitter pre-emphasis and de-emphasis

    • Dynamic reconfiguration of individual transceiver channels


    Configuration

    • Tamper protection—comprehensive design protection to protect your valuable IP investments

    • Enhanced 256-bit advanced encryption standard (AES) design security with authentication

    • Configuration via protocol (CvP) using PCIe Gen1 or Gen2

    • Dynamic reconfiguration of the transceivers and PLLs

    • Fine-grained partial reconfiguration of the core fabric

    • Active Serial ×4 Interface


    Power management

    • Programmable Power Technology

    • Intel Quartus® Prime Pro Edition integrated power analysis tool


    Software and tools

    • Intel Quartus Prime Pro Edition design suite

    • Transceiver toolkit

    • Platform Designer (Standard) system integration tool

    • DSP Builder advanced blockset

    • OpenCL* support


    Chip Altera Cyclone naming rules,Chinese chip Will replace it






    PDF

    7020
    672-BGA
    EP2AGX260EF29C6
    Arria II GX Field Programmable Gate Array (FPGA) IC 372 12038144 244188 780-BBGA, FCBGA
    7315
    780-BBGA, FCBGA
    5CSEMA4U23C6N
    Dual ARM® Cortex®-A9 MPCore™ with CoreSight™ System On Chip (SOC) IC Cyclone® V SE FPGA - 40K Logic Elements 925MHz 672-UBGA (23x23)
    9367
    672-FBGA
    5SGXEB6R2F43I2G
    Stratix® V GX Field Programmable Gate Array (FPGA) IC 600 53248000 597000 1760-BBGA, FCBGA
    4311
    1760-BBGA, FCBGA
    A Comprehensive Guide to 10CL040YU484A7G Cyclone® 10 LP Field Programmable Gate Array (FPGA) IC

    Cyclone® 10 LP Field Programmable Gate Array (FPGA) IC 325 1161216 39600 484-FBGA


    Operating Conditions

    When Intel Cyclone 10 LP devices are implemented in a system, they are rated according to a set of defined parameters.

    To maintain the highest possible performance and reliability of Intel Cyclone 10 LP devices, you must consider the operating

    requirements described in this document. Intel Cyclone 10 LP devices are offered in commercial, industrial, extended

    industrial and, automotive grades as follows:

    • –6 (fastest) and –8 speed grades for commercial devices

    • –7 and –8 speed grades for industrial devices

    • –7 speed grade for automotive devices

    Intel Cyclone 10 LP devices are offered in the following core voltages:

    • Lower core voltage option (1.0 V)—"Z": For –I8 speed grade

    • Standard core voltage option (1.2 V)—"Y": For –C6, –C8, –I7, and –A7 speed grades

    A prefix associated with the operating temperature range is attached to the speed grades:

    • Commercial with a "C" prefix: –C6, –C8

    • Industrial with an "I" prefix: –I7, –I8

    • Automotive with an "A" prefix: –A7


    Chip Altera Cyclone naming rules,Chinese chip Will replace it






    PDF

    1607
    484-FBGA

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