Intel

Cyclone® IV E Field Programmable Gate Array (FPGA) IC 532 608256 28848 780-BGA

Operating Conditions

When Cyclone IV devices are implemented in a system, they are rated according to a

set of defined parameters. To maintain the highest possible performance and

reliability of Cyclone IV devices, you must consider the operating requirements

described in this chapter.

Cyclone IV devices are offered in commercial, industrial, extended industrial and,

automotive grades. Cyclone IV E devices offer –6 (fastest), –7, –8, –8L, and –9L speed

grades for commercial devices, –8L speed grades for industrial devices, and –7 speed

grade for extended industrial and automotive devices. Cyclone IV GX devices offer

–6 (fastest), –7, and –8 speed grades for commercial devices and –7 speed grade for

industrial devices.

Cyclone IV E devices are offered in core voltages of 1.0 and 1.2 V. Cyclone IV E

devices with a core voltage of 1.0 V have an ‘L’ prefix attached to the speed grade.

In this chapter, a prefix associated with the operating temperature range is attached to

the speed grades; commercial with a “C” prefix, industrial with an “I” prefix, and

automotive with an “A” prefix. Therefore, commercial devices are indicated as C6, C7,

C8, C8L, or C9L per respective speed grade. Industrial devices are indicated as I7, I8,

or I8L. Automotive devices are indicated as A7.

Cyclone IV E industrial devices I7 are offered with extended operating temperature range.

Chip Altera Cyclone naming rules，Chinese chip Will replace it

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Cyclone® IV GX Field Programmable Gate Array (FPGA) IC 150 774144 21280 324-LBGA

Introduction

The CycloneTM field programmable gate array family is based ona 1.5-V,

0.13-um, alayer copper SRAM process, with densities up to 20,060 logic

elements (LEs) and up to 288 Kbits of RAM. With features like phase-

locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

interface to meet DDR SDRAM and fast cycle RAM (FCRAM) memory

requirements, Cyclone devices are a cost effective solution for data-path

applications. Cyclone devices support various I/O standards, including

LVDS at data rates up to 311 megabits per second (Mbps) and 66-MHz,

32-bit peripheral component interconnect (PCI), for interfacing with and

supporting ASSP and ASIC devices. Altera also offers new low-cost serial

configuration devices to configure Cyclone devices.

Features

■Up to 294,912 RAM bits (36,864 bytes)

■Supports configuration through low-cost serial configuration device

■Support for LVTTL, LVCMOS, SSTL-2, and SSTL-3 I/O standards

■Support for 66-MHz, 32-bit PCI standard

■Low speed (311 Mbps) LVDS 1/O support

■Up to two PLLs per device provide clock multiplication and phase shifting

■Up to eight global clock lines with six clock resources available per

logic array block (LAB) row

■Support for external memory, induding DDR SDRAM (133 MHz),

FCRAM, and single data rate (SDR) SDRAM

■Support for multiple intellectual property (IP) cores, including

Altera" MegaCore functions and Altera Megafunctions Partners

Program (AMPPSM) megafunctions

Chip Altera Cyclone naming rules，Chinese chip Will replace it

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Cyclone® V E Field Programmable Gate Array (FPGA) IC 224 3464192 49000 484-BGA

Summary of Features for Cyclone V Devices

Technology

• TSMC's 28-nm low-power (28LP) process technology

• 1.1 V core voltage

Packaging

• Wirebond low-halogen packages

• Multiple device densities with compatible package footprints for seamless migration between

different device densities

• RoHS-compliant and leaded(1)options

High-performance FPGA fabric

Enhanced 8-input ALM with four registers

Internal memory blocks

• M10K—10-kilobits (Kb) memory blocks with soft error correction code (ECC)

• Memory logic array block (MLAB)—640-bit distributed LUTRAM where you can use up to 25%

of the ALMs as MLAB memory

Embedded Hard IP blocks

Variable-precision DSP

• Native support for up to three signal processing precision levels

(three 9 x 9, two 18 x 18, or one 27 x 27 multiplier) in the same

variable-precision DSP block

• 64-bit accumulator and cascade

• Embedded internal coefficient memory

• Preadder/subtractor for improved efficiency

Memory controller

DDR3, DDR2, and LPDDR2 with 16 and 32 bit ECC support

Embedded transceiver I/O

PCI Express* (PCIe*) Gen2 and Gen1 (x1, x2, or x4) hard IP with

multifunction support, endpoint, and root port

Clock networks

• Up to 550 MHz global clock network

• Global, quadrant, and peripheral clock networks

• Clock networks that are not used can be powered down to reduce dynamic power

Phase-locked loops (PLLs)

• Precision clock synthesis, clock delay compensation, and zero delay buffering (ZDB)

• Integer mode and fractional mode

FPGA General-purpose I/Os (GPIOs)

• 875 megabits per second (Mbps) LVDS receiver and 840 Mbps LVDS transmitter

• 400 MHz/800 Mbps external memory interface

• On-chip termination (OCT)

• 3.3 V support with up to 16 mA drive strength

Low-power high-speed serial interface

• 614 Mbps to 6.144 Gbps integrated transceiver speed

• Transmit pre-emphasis and receiver equalization

• Dynamic partial reconfiguration of individual channels

HPS(Cyclone V SE, SX,and ST devices only)

• Single or dual-core Arm Cortex-A9 MPCore processor-up to 925 MHz maximum frequency with

support for symmetric and asymmetric multiprocessing

• Interface peripherals—10/100/1000 Ethernet media access control (EMAC), USB 2.0

On-The-GO (OTG) controller, quad serial peripheral interface (QSPI) flash controller, NAND

flash controller, Secure Digital/MultiMediaCard (SD/MMC) controller, UART, controller area

network (CAN), serial peripheral interface (SPI), I2C interface, and up to 85 HPS GPIO

interfaces

• System peripherals—general-purpose timers, watchdog timers, direct memory access (DMA)

controller, FPGA configuration manager, and clock and reset managers

• On-chip RAM and boot ROM

• HPS–FPGA bridges—include the FPGA-to-HPS, HPS-to-FPGA, and lightweight HPS-to-FPGA

bridges that allow the FPGA fabric to issue transactions to slaves in the HPS, and vice versa

• FPGA-to-HPS SDRAM controller subsystem—provides a configurable interface to the multiport

front end (MPFE) of the HPS SDRAM controller

• Arm CoreSight™ JTAG debug access port, trace port, and on-chip trace storage

Configuration

• Tamper protection—comprehensive design protection to protect your valuable IP investments

• Enhanced advanced encryption standard (AES) design security features

• CvP

• Dynamic reconfiguration of the FPGA

• Active serial (AS) x1 and x4, passive serial (PS), JTAG, and fast passive parallel (FPP) x8 and

x16 configuration options

• Internal scrubbing (2)

• Partial reconfiguration (3)

How to choose FPGA for your project?

PDF

Cyclone® 10 LP Field Programmable Gate Array (FPGA) IC 88 276480 6272 144-LQFP Exposed Pad

Summary of Features for Intel Cyclone 10 LP Devices

Technology 

• Low-cost, low-power FPGA fabric

• 1.0 V and 1.2 V core voltage options

• Available in commercial, industrial, and automotive temperature grades

Packaging

• Several package types and footprints:

— FineLine BGA (FBGA)

— Enhanced Thin Quad Flat Pack (EQFP)

— Ultra FineLine BGA (UBGA)

— Micro FineLine BGA (MBGA)

• Multiple device densities with pin migration capability

• RoHS6 compliance

Core architecture

• Logic elements (LEs)—four-input look-up table (LUT) and register

• Abundant routing/metal interconnect between all LEs

Internal memory blocks

• M9K—9-kilobits (Kb) of embedded SRAM memory blocks, cascadable

• Configurable as RAM (single-port, simple dual port, or true dual port), FIFO buffers, or ROM

Embedded multiplier blocks

• One 18 × 18 or two 9 × 9 multiplier modes, cascadable

• Complete suite of DSP IPs for algorithmic acceleration

Clock networks

• Global clocks that drive throughout entire device, feeding all device quadrants

• Up to 15 dedicated clock pins that can drive up to 20 global clocks

Phase-locked loops (PLLs)

• Up to four general purpose PLLs

• Provides robust clock management and synthesis

General-purpose I/Os (GPIOs)

• Multiple I/O standards support

• Programmable I/O features

• True LVDS and emulated LVDS transmitters and receivers

• On-chip termination (OCT)

SEU mitigation

SEU detection during configuration and operation

Configuration

• Active serial (AS), passive serial (PS), fast passive parallel (FPP)

• JTAG configuration scheme

• Configuration data decompression

• Remote system upgrade

Chip Altera Cyclone naming rules，Chinese chip Will replace it

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MAX® 10 Field Programmable Gate Array (FPGA) IC 130 387072 8000 169-LFBGA

Intel® MAX® 10 FPGA Device Overview

Intel® MAX® 10 devices are single-chip, non-volatile low-cost programmable logic

devices (PLDs) to integrate the optimal set of system components.

The highlights of the Intel MAX 10 devices include:

• Internally stored dual configuration flash

• User flash memory

• Instant on support

• Integrated analog-to-digital converters (ADCs)

• Single-chip Nios II soft core processor support

Intel MAX 10 devices are the ideal solution for system management, I/O expansion,

communication control planes, industrial, automotive, and consumer applications.

Supporting Feature

Secure on-die flash memory enables device configuration in less than 10 ms

• Single device integrating PLD logic, RAM, flash memory, digital signal processing (DSP), ADC, phase-locked loop (PLL), and I/Os

• Small packages available from 3 mm × 3 mm

• Sleep mode—significant standby power reduction and resumption in less than 1 ms

• Longer battery life—resumption from full power-off in less than 10 ms

Built on TSMC's 55 nm embedded flash process technology

• Intel Quartus® Prime Lite edition (no cost license)

• Platform Designer (Standard) system integration tool

• DSP Builder for Intel FPGAs

• Nios® II Embedded Design Suite (EDS)

How to choose FPGA for your project?

Cyclone® V GT Field Programmable Gate Array (FPGA) IC 224 5001216 77000 484-FBGA

Summary of Features for Cyclone V Devices

Technology

• TSMC's 28-nm low-power (28LP) process technology

• 1.1 V core voltage

Packaging

• Wirebond low-halogen packages

• Multiple device densities with compatible package footprints for seamless migration between

different device densities

• RoHS-compliant and leaded(1)options

High-performance FPGA fabric

Enhanced 8-input ALM with four registers

Internal memory blocks

• M10K—10-kilobits (Kb) memory blocks with soft error correction code (ECC)

• Memory logic array block (MLAB)—640-bit distributed LUTRAM where you can use up to 25%

of the ALMs as MLAB memory

Embedded Hard IP blocks

Variable-precision DSP

• Native support for up to three signal processing precision levels

(three 9 x 9, two 18 x 18, or one 27 x 27 multiplier) in the same

variable-precision DSP block

• 64-bit accumulator and cascade

• Embedded internal coefficient memory

• Preadder/subtractor for improved efficiency

Memory controller

DDR3, DDR2, and LPDDR2 with 16 and 32 bit ECC support

Embedded transceiver I/O

PCI Express* (PCIe*) Gen2 and Gen1 (x1, x2, or x4) hard IP with

multifunction support, endpoint, and root port

Clock networks

• Up to 550 MHz global clock network

• Global, quadrant, and peripheral clock networks

• Clock networks that are not used can be powered down to reduce dynamic power

Phase-locked loops (PLLs)

• Precision clock synthesis, clock delay compensation, and zero delay buffering (ZDB)

• Integer mode and fractional mode

FPGA General-purpose I/Os (GPIOs)

• 875 megabits per second (Mbps) LVDS receiver and 840 Mbps LVDS transmitter

• 400 MHz/800 Mbps external memory interface

• On-chip termination (OCT)

• 3.3 V support with up to 16 mA drive strength

Low-power high-speed serial interface

• 614 Mbps to 6.144 Gbps integrated transceiver speed

• Transmit pre-emphasis and receiver equalization

• Dynamic partial reconfiguration of individual channels

HPS(Cyclone V SE, SX,and ST devices only)

• Single or dual-core Arm Cortex-A9 MPCore processor-up to 925 MHz maximum frequency with

support for symmetric and asymmetric multiprocessing

• Interface peripherals—10/100/1000 Ethernet media access control (EMAC), USB 2.0

On-The-GO (OTG) controller, quad serial peripheral interface (QSPI) flash controller, NAND

flash controller, Secure Digital/MultiMediaCard (SD/MMC) controller, UART, controller area

network (CAN), serial peripheral interface (SPI), I2C interface, and up to 85 HPS GPIO

interfaces

• System peripherals—general-purpose timers, watchdog timers, direct memory access (DMA)

controller, FPGA configuration manager, and clock and reset managers

• On-chip RAM and boot ROM

• HPS–FPGA bridges—include the FPGA-to-HPS, HPS-to-FPGA, and lightweight HPS-to-FPGA

bridges that allow the FPGA fabric to issue transactions to slaves in the HPS, and vice versa

• FPGA-to-HPS SDRAM controller subsystem—provides a configurable interface to the multiport

front end (MPFE) of the HPS SDRAM controller

• Arm CoreSight™ JTAG debug access port, trace port, and on-chip trace storage

Configuration

• Tamper protection—comprehensive design protection to protect your valuable IP investments

• Enhanced advanced encryption standard (AES) design security features

• CvP

• Dynamic reconfiguration of the FPGA

• Active serial (AS) x1 and x4, passive serial (PS), JTAG, and fast passive parallel (FPP) x8 and

x16 configuration options

• Internal scrubbing (2)

• Partial reconfiguration (3)

Cyclone® V GT Field Programmable Gate Array (FPGA) IC 240 7880704 149500 484-FBGA

Summary of Features for Cyclone V Devices

Technology

• TSMC's 28-nm low-power (28LP) process technology

• 1.1 V core voltage

Packaging

• Wirebond low-halogen packages

• Multiple device densities with compatible package footprints for seamless migration between

different device densities

• RoHS-compliant and leaded(1)options

High-performance FPGA fabric

Enhanced 8-input ALM with four registers

Internal memory blocks

• M10K—10-kilobits (Kb) memory blocks with soft error correction code (ECC)

• Memory logic array block (MLAB)—640-bit distributed LUTRAM where you can use up to 25%

of the ALMs as MLAB memory

Embedded Hard IP blocks

Variable-precision DSP

• Native support for up to three signal processing precision levels

(three 9 x 9, two 18 x 18, or one 27 x 27 multiplier) in the same

variable-precision DSP block

• 64-bit accumulator and cascade

• Embedded internal coefficient memory

• Preadder/subtractor for improved efficiency

Memory controller

DDR3, DDR2, and LPDDR2 with 16 and 32 bit ECC support

Embedded transceiver I/O

PCI Express* (PCIe*) Gen2 and Gen1 (x1, x2, or x4) hard IP with

multifunction support, endpoint, and root port

Clock networks

• Up to 550 MHz global clock network

• Global, quadrant, and peripheral clock networks

• Clock networks that are not used can be powered down to reduce dynamic power

Phase-locked loops (PLLs)

• Precision clock synthesis, clock delay compensation, and zero delay buffering (ZDB)

• Integer mode and fractional mode

FPGA General-purpose I/Os (GPIOs)

• 875 megabits per second (Mbps) LVDS receiver and 840 Mbps LVDS transmitter

• 400 MHz/800 Mbps external memory interface

• On-chip termination (OCT)

• 3.3 V support with up to 16 mA drive strength

Low-power high-speed serial interface

• 614 Mbps to 6.144 Gbps integrated transceiver speed

• Transmit pre-emphasis and receiver equalization

• Dynamic partial reconfiguration of individual channels

HPS(Cyclone V SE, SX,and ST devices only)

• Single or dual-core Arm Cortex-A9 MPCore processor-up to 925 MHz maximum frequency with

support for symmetric and asymmetric multiprocessing

• Interface peripherals—10/100/1000 Ethernet media access control (EMAC), USB 2.0

On-The-GO (OTG) controller, quad serial peripheral interface (QSPI) flash controller, NAND

flash controller, Secure Digital/MultiMediaCard (SD/MMC) controller, UART, controller area

network (CAN), serial peripheral interface (SPI), I2C interface, and up to 85 HPS GPIO

interfaces

• System peripherals—general-purpose timers, watchdog timers, direct memory access (DMA)

controller, FPGA configuration manager, and clock and reset managers

• On-chip RAM and boot ROM

• HPS–FPGA bridges—include the FPGA-to-HPS, HPS-to-FPGA, and lightweight HPS-to-FPGA

bridges that allow the FPGA fabric to issue transactions to slaves in the HPS, and vice versa

• FPGA-to-HPS SDRAM controller subsystem—provides a configurable interface to the multiport

front end (MPFE) of the HPS SDRAM controller

• Arm CoreSight™ JTAG debug access port, trace port, and on-chip trace storage

Configuration

• Tamper protection—comprehensive design protection to protect your valuable IP investments

• Enhanced advanced encryption standard (AES) design security features

• CvP

• Dynamic reconfiguration of the FPGA

• Active serial (AS) x1 and x4, passive serial (PS), JTAG, and fast passive parallel (FPP) x8 and

x16 configuration options

• Internal scrubbing (2)

• Partial reconfiguration (3)

MAX® 10 Field Programmable Gate Array (FPGA) IC 130 562176 16000 169-LFBGA

Intel® MAX® 10 FPGA Device Datasheet

This datasheet describes the electrical characteristics, switching characteristics, configuration specifications, and timing for

Intel MAX® 10 devices.

Intel MAX 10 Device Grades and Speed Grades Supported

Commercial

• –C7

• –C8 (slowest)

Industrial

• –I6 (fastest)

• –I7

Automotive

• –A6

• –A7