Intel

Cyclone® 10 LP Field Programmable Gate Array (FPGA) IC 321 2396160 55856 484-BGA

Intel® Cyclone® 10 LP Device Overview

The Intel® Intel Cyclone® 10 LP FPGAs are optimized for low cost and low static

power, making them ideal for high-volume and cost-sensitive applications.

Intel Cyclone 10 LP devices provide a high density sea of programmable gates, onboard resources, and general purpose I/Os. These resources satisfies the

requirements of I/O expansion and chip-to-chip interfacing. The Intel Cyclone 10 LP

architecture suits smart and connected end applications across many market

segments:

• Industrial and automotive

• Broadcast, wireline, and wireless

• Compute and storage

• Government, military, and aerospace

• Medical, consumer, and smart energy

The free but powerful Intel Quartus® Prime Lite Edition software suite of design tools

meets the requirements of several classes of users:

• Existing FPGA designers

• Embedded designers using the FPGA with Nios® II processor

• Students and hobbyists who are new to FPGA

Summary of Features for Intel Cyclone 10 LP Devices

Technology

• Low-cost, low-power FPGA fabric

• 1.0 V and 1.2 V core voltage options

• Available in commercial, industrial, and automotive temperature grades

Packaging

• Several package types and footprints:

— FineLine BGA (FBGA)

— Enhanced Thin Quad Flat Pack (EQFP)

— Ultra FineLine BGA (UBGA)

— Micro FineLine BGA (MBGA)

• Multiple device densities with pin migration capability

• RoHS6 compliance

Core architecture

• Logic elements (LEs)—four-input look-up table (LUT) and register

• Abundant routing/metal interconnect between all LEs

Internal memory blocks

• M9K—9-kilobits (Kb) of embedded SRAM memory blocks, cascadable

• Configurable as RAM (single-port, simple dual port, or true dual port), FIFO buffers, or ROM

Embedded multiplier blocks

• One 18 × 18 or two 9 × 9 multiplier modes, cascadable

• Complete suite of DSP IPs for algorithmic acceleration

Clock networks

• Global clocks that drive throughout entire device, feeding all device quadrants

• Up to 15 dedicated clock pins that can drive up to 20 global clocks

Phase-locked loops (PLLs)

• Up to four general purpose PLLs

• Provides robust clock management and synthesis

General-purpose I/Os (GPIOs)

• Multiple I/O standards support

• Programmable I/O features

• True LVDS and emulated LVDS transmitters and receivers

• On-chip termination (OCT)

SEU mitigation

SEU detection during configuration and operation

Configuration

• Active serial (AS), passive serial (PS), fast passive parallel (FPP)

• JTAG configuration scheme

• Configuration data decompression

• Remote system upgrade

How to choose FPGA for your project?

Dual ARM® Cortex®-A9 MPCore™ with CoreSight™ System On Chip (SOC) IC Cyclone® V SE FPGA - 40K Logic Elements 600MHz 484-UBGA (19x19)

Summary of Features for Cyclone V Devices

Technology

• TSMC's 28-nm low-power (28LP) process technology

• 1.1 V core voltage

Packaging

• Wirebond low-halogen packages

• Multiple device densities with compatible package footprints for seamless migration between

different device densities

• RoHS-compliant and leaded(1)options

High-performance FPGA fabric

Enhanced 8-input ALM with four registers

Internal memory blocks

• M10K—10-kilobits (Kb) memory blocks with soft error correction code (ECC)

• Memory logic array block (MLAB)—640-bit distributed LUTRAM where you can use up to 25%

of the ALMs as MLAB memory

Embedded Hard IP blocks

Variable-precision DSP

• Native support for up to three signal processing precision levels

(three 9 x 9, two 18 x 18, or one 27 x 27 multiplier) in the same

variable-precision DSP block

• 64-bit accumulator and cascade

• Embedded internal coefficient memory

• Preadder/subtractor for improved efficiency

Memory controller

DDR3, DDR2, and LPDDR2 with 16 and 32 bit ECC support

Embedded transceiver I/O

PCI Express* (PCIe*) Gen2 and Gen1 (x1, x2, or x4) hard IP with

multifunction support, endpoint, and root port

Clock networks

• Up to 550 MHz global clock network

• Global, quadrant, and peripheral clock networks

• Clock networks that are not used can be powered down to reduce dynamic power

Phase-locked loops (PLLs)

• Precision clock synthesis, clock delay compensation, and zero delay buffering (ZDB)

• Integer mode and fractional mode

FPGA General-purpose I/Os (GPIOs)

• 875 megabits per second (Mbps) LVDS receiver and 840 Mbps LVDS transmitter

• 400 MHz/800 Mbps external memory interface

• On-chip termination (OCT)

• 3.3 V support with up to 16 mA drive strength

Low-power high-speed serial interface

• 614 Mbps to 6.144 Gbps integrated transceiver speed

• Transmit pre-emphasis and receiver equalization

• Dynamic partial reconfiguration of individual channels

HPS(Cyclone V SE, SX,and ST devices only)

• Single or dual-core Arm Cortex-A9 MPCore processor-up to 925 MHz maximum frequency with

support for symmetric and asymmetric multiprocessing

• Interface peripherals—10/100/1000 Ethernet media access control (EMAC), USB 2.0

On-The-GO (OTG) controller, quad serial peripheral interface (QSPI) flash controller, NAND

flash controller, Secure Digital/MultiMediaCard (SD/MMC) controller, UART, controller area

network (CAN), serial peripheral interface (SPI), I2C interface, and up to 85 HPS GPIO

interfaces

• System peripherals—general-purpose timers, watchdog timers, direct memory access (DMA)

controller, FPGA configuration manager, and clock and reset managers

• On-chip RAM and boot ROM

• HPS–FPGA bridges—include the FPGA-to-HPS, HPS-to-FPGA, and lightweight HPS-to-FPGA

bridges that allow the FPGA fabric to issue transactions to slaves in the HPS, and vice versa

• FPGA-to-HPS SDRAM controller subsystem—provides a configurable interface to the multiport

front end (MPFE) of the HPS SDRAM controller

• Arm CoreSight™ JTAG debug access port, trace port, and on-chip trace storage

Configuration

• Tamper protection—comprehensive design protection to protect your valuable IP investments

• Enhanced advanced encryption standard (AES) design security features

• CvP

• Dynamic reconfiguration of the FPGA

• Active serial (AS) x1 and x4, passive serial (PS), JTAG, and fast passive parallel (FPP) x8 and

x16 configuration options

• Internal scrubbing (2)

• Partial reconfiguration (3)