Lattice Semiconductor Corporation

LFXP3C-5Q208C

XP Field Programmable Gate Array (FPGA) IC 136 55296 3000 208-BFQFP

4145

208-BFQFP

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LFXP3E-3T100C

XP Field Programmable Gate Array (FPGA) IC 62 55296 3000 100-LQFP

1335

100-LQFP

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ISPLSI 2064VE-135LTN44

IC CPLD 64MC 7.5NS 44TQFP

4806

44-TQFP

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ICE40LP640-CM49

iCE40™ LP Field Programmable Gate Array (FPGA) IC 35 32768 640 49-VFBGA

5747

49-VFBGA

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ICE40LP640-CM36

iCE40™ LP Field Programmable Gate Array (FPGA) IC 25 32768 640 36-VFBGA

7512

36-VFBGA

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ICE40HX640-VQ100

iCE40™ HX Field Programmable Gate Array (FPGA) IC 67 32768 640 100-LQFP

7294

100-LQFP

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ICE40LP1K-QN84

iCE40™ LP Field Programmable Gate Array (FPGA) IC 67 65536 1280 84-VFQFN Dual Rows, Exposed Pad

3

84-VFQFN Dual Rows, Exposed Pad

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ICE40HX1K-TQ144

iCE40™ HX Field Programmable Gate Array (FPGA) IC 96 65536 1280 144-LQFP

2

144-LQFP

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ICE40HX1K-CB132

iCE40™ HX Field Programmable Gate Array (FPGA) IC 95 65536 1280 132-LFBGA, CSPBGA

524

132-LFBGA, CSPBGA

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ICE40LP4K-CM225

iCE40™ LP Field Programmable Gate Array (FPGA) IC 167 81920 3520 225-VFBGA

8305

225-VFBGA

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ICE40LP4K-CM81

iCE40™ LP Field Programmable Gate Array (FPGA) IC 63 81920 3520 81-VFBGA

1480

81-VFBGA

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ICE40HX4K-CB132

iCE40™ HX Field Programmable Gate Array (FPGA) IC 95 81920 3520 132-LFBGA, CSPBGA

1

132-LFBGA, CSPBGA

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ICE40HX4K-TQ144

<p><span style="font-family: 隶书, SimLi; font-size: 18px;">iCE40™ HX Field Programmable Gate Array (FPGA) IC 107 81920 3520 144-LQFP</span></p><p><br/></p><p><span style="text-decoration: underline; color: rgb(0, 176, 240);"><strong><span style="text-decoration: underline; text-wrap: nowrap; font-family: 隶书, SimLi; font-size: 18px;">General Description</span></strong></span></p><p><span style="text-wrap: nowrap; font-family: 隶书, SimLi; font-size: 18px;">The iCE40 family architecture contains an array of Programmable Logic Blocks (PLB), sysCLOCK™ PLLs, Nonvolatile</span></p><p><span style="text-wrap: nowrap; font-family: 隶书, SimLi; font-size: 18px;">Programmable Configuration Memory (NVCM) and blocks of sysMEM™ Embedded Block RAM (EBR) surrounded by</span></p><p><span style="text-wrap: nowrap; font-family: 隶书, SimLi; font-size: 18px;">Programmable I/O (PIO).&nbsp;</span></p><p><span style="text-wrap: nowrap; font-family: 隶书, SimLi; font-size: 18px;">The logic blocks, Programmable Logic Blocks (PLB) and sysMEM EBR blocks, are arranged in a two-dimensional grid with</span></p><p><span style="text-wrap: nowrap; font-family: 隶书, SimLi; font-size: 18px;">rows and columns. Each column has either logic blocks or EBR blocks. The PIO cells are located at the periphery of the</span></p><p><span style="text-wrap: nowrap; font-family: 隶书, SimLi; font-size: 18px;">device, arranged in banks. The PLB contains the building blocks for logic, arithmetic, and register functions. The PIOs</span></p><p><span style="text-wrap: nowrap; font-family: 隶书, SimLi; font-size: 18px;">utilize a flexible I/O buffer referred to as a sysIO buffer that supports operation with a variety of interface standards. The</span></p><p><span style="text-wrap: nowrap; font-family: 隶书, SimLi; font-size: 18px;">blocks are connected with many vertical and horizontal routing channel resources. Theplace and route software tool</span></p><p><span style="text-wrap: nowrap; font-family: 隶书, SimLi; font-size: 18px;">automatically allocates these routing resources.</span></p><p><span style="text-wrap: nowrap; font-family: 隶书, SimLi; font-size: 18px;">In the iCE40 family, there are up to four independent sysIO banks. Note on some packages VCCIO banks are tied together.</span></p><p><span style="text-wrap: nowrap; font-family: 隶书, SimLi; font-size: 18px;">There are different types of I/O buffers on the different banks. Refer to the details in later sections of this document.</span></p><p><span style="text-wrap: nowrap; font-family: 隶书, SimLi; font-size: 18px;">The sysMEM EBRs are large 4 kbit, dedicated fast memory blocks. These blocks can be configured as RAM, ROM or FIFO.</span></p><p><span style="text-wrap: nowrap; font-family: 隶书, SimLi; font-size: 18px;">The iCE40 architecture also provides up to two sysCLOCK Phase Locked Loop (PLL) blocks. The PLLs have multiply, divide,</span></p><p><span style="text-wrap: nowrap; font-family: 隶书, SimLi; font-size: 18px;">and phase shifting capabilities that are used to manage the frequency and phase relationships of the clocks.</span></p><p><span style="text-wrap: nowrap; font-family: 隶书, SimLi; font-size: 18px;">Every device in the family has a SPI port that supports programming and configuration of the device. The iCE40 includes</span></p><p><span style="text-wrap: nowrap; font-family: 隶书, SimLi; font-size: 18px;">on-chip, Nonvolatile Configuration Memory (NVCM).</span></p><p><span style="text-wrap: nowrap; font-family: 隶书, SimLi; font-size: 18px;"><br/></span></p><p><span style="text-decoration: underline; color: rgb(0, 176, 240);"><strong><span style="text-decoration: underline; text-wrap: nowrap; font-family: 隶书, SimLi; font-size: 18px;">Features</span></strong></span></p><ul style="list-style-type: disc;"><li><p><span style="text-wrap: nowrap; font-family: 隶书, SimLi; font-size: 18px;">Flexible Logic Architecture</span></p></li></ul><p><span style="text-wrap: nowrap; font-family: 隶书, SimLi; font-size: 18px;">&nbsp; &nbsp; &nbsp; Five devices with 384 to 7,680 LUT4s and 10 to 206 I/Os</span></p><ul style="list-style-type: disc;"><li><p><span style="text-wrap: nowrap; font-family: 隶书, SimLi; font-size: 18px;">Ultra Low Power Devices</span></p></li></ul><p><span style="text-wrap: nowrap; font-family: 隶书, SimLi; font-size: 18px;">&nbsp; &nbsp; &nbsp; Advanced 40 nm low power process</span></p><p><span style="text-wrap: nowrap; font-family: 隶书, SimLi; font-size: 18px;">&nbsp; &nbsp; &nbsp; As low as 21 µA standby power</span></p><p><span style="text-wrap: nowrap; font-family: 隶书, SimLi; font-size: 18px;">&nbsp; &nbsp; &nbsp; Programmable low swing differential I/Os</span></p><ul style="list-style-type: disc;"><li><p><span style="text-wrap: nowrap; font-family: 隶书, SimLi; font-size: 18px;">Embedded and Distributed Memory</span></p></li></ul><p><span style="text-wrap: nowrap; font-family: 隶书, SimLi; font-size: 18px;">&nbsp; &nbsp; &nbsp; Up to 128 kbits sysMEM™ Embedded Block RAM</span></p><ul style="list-style-type: disc;"><li><p><span style="text-wrap: nowrap; font-family: 隶书, SimLi; font-size: 18px;">Pre-Engineered Source Synchronous I/O</span></p></li></ul><p><span style="text-wrap: nowrap; font-family: 隶书, SimLi; font-size: 18px;">&nbsp; &nbsp; &nbsp; DDR registers in I/O cells</span></p><ul style="list-style-type: disc;"><li><p><span style="text-wrap: nowrap; font-family: 隶书, SimLi; font-size: 18px;">High Current LED Drivers</span></p></li></ul><p><span style="text-wrap: nowrap; font-family: 隶书, SimLi; font-size: 18px;">&nbsp; &nbsp; &nbsp; Three High Current Drivers used for three different LEDs or one RGB LED</span></p><ul style="list-style-type: disc;"><li><p><span style="text-wrap: nowrap; font-family: 隶书, SimLi; font-size: 18px;">High Performance, Flexible I/O Buffer</span></p></li></ul><p><span style="text-wrap: nowrap; font-family: 隶书, SimLi; font-size: 18px;">&nbsp; &nbsp; &nbsp; Programmable sysIO™ buffer supports wide range of interfaces:</span></p><p><span style="text-wrap: nowrap; font-family: 隶书, SimLi; font-size: 18px;">&nbsp; &nbsp; &nbsp; — LVCMOS 3.3/2.5/1.8</span></p><p><span style="text-wrap: nowrap; font-family: 隶书, SimLi; font-size: 18px;">&nbsp; &nbsp; &nbsp; — LVDS25E, subLVDS</span></p><p><span style="text-wrap: nowrap; font-family: 隶书, SimLi; font-size: 18px;">&nbsp; &nbsp; &nbsp; — Schmitt trigger inputs, to 200 mV typical hysteresis</span></p><p><span style="text-wrap: nowrap; font-family: 隶书, SimLi; font-size: 18px;">&nbsp; &nbsp; &nbsp; Programmable pull-up mode</span></p><ul style="list-style-type: disc;"><li><p><span style="text-wrap: nowrap; font-family: 隶书, SimLi; font-size: 18px;">Flexible On-Chip Clocking</span></p></li></ul><p><span style="text-wrap: nowrap; font-family: 隶书, SimLi; font-size: 18px;">&nbsp; &nbsp; &nbsp; Eight low-skew global clock resources</span></p><p><span style="text-wrap: nowrap; font-family: 隶书, SimLi; font-size: 18px;">&nbsp; &nbsp; &nbsp; Up to two analog PLLs per device</span></p><ul style="list-style-type: disc;"><li><p><span style="text-wrap: nowrap; font-family: 隶书, SimLi; font-size: 18px;">Flexible Device Configuration</span></p></li></ul><p><span style="text-wrap: nowrap; font-family: 隶书, SimLi; font-size: 18px;">&nbsp; &nbsp; &nbsp; SRAM is configured through:</span></p><p><span style="text-wrap: nowrap; font-family: 隶书, SimLi; font-size: 18px;">&nbsp; &nbsp; &nbsp; — Standard SPI Interface</span></p><p><span style="text-wrap: nowrap; font-family: 隶书, SimLi; font-size: 18px;">&nbsp; &nbsp; &nbsp; — Internal Nonvolatile Configuration Memory (NVCM)</span></p><ul style="list-style-type: disc;"><li><p><span style="text-wrap: nowrap; font-family: 隶书, SimLi; font-size: 18px;">Broad Range of Package Options</span></p></li></ul><p><span style="text-wrap: nowrap; font-family: 隶书, SimLi; font-size: 18px;">&nbsp; &nbsp; &nbsp; WLCSP, QFN, VQFP, TQFP, ucBGA, caBGA,and csBGA package options</span></p><p><span style="text-wrap: nowrap; font-family: 隶书, SimLi; font-size: 18px;">&nbsp; &nbsp; &nbsp; Small footprint package options</span></p><p><span style="text-wrap: nowrap; font-family: 隶书, SimLi; font-size: 18px;">&nbsp; &nbsp; &nbsp; — As small as 1.40 mm x 1.48 mm</span></p><p><span style="text-wrap: nowrap; font-family: 隶书, SimLi; font-size: 18px;">&nbsp; &nbsp; &nbsp; Advanced halogen-free packaging</span></p><p><br/></p>

110

144-LQFP

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ICE40HX8K-CB132

iCE40™ HX Field Programmable Gate Array (FPGA) IC 95 131072 7680 132-LFBGA, CSPBGA

810

132-LFBGA, CSPBGA

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LCMXO2-1200UHC-6FTG256C

MachXO2 Field Programmable Gate Array (FPGA) IC 206 75776 1280 256-LBGA

5121

256-LBGA

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LCMXO2-1200UHC-6FTG256I

MachXO2 Field Programmable Gate Array (FPGA) IC 206 75776 1280 256-LBGA

2211

256-LBGA

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GAL22V10D-15LPI

IC CPLD 10MC 15NS 24DIP

2945

24-DIP (0.300", 7.62mm)

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LCMXO2-256HC-5SG32C

MachXO2 Field Programmable Gate Array (FPGA) IC 21 256 32-UFQFN Exposed Pad

931

32-UFQFN Exposed Pad

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LCMXO2-256HC-5SG32I

MachXO2 Field Programmable Gate Array (FPGA) IC 21 256 32-UFQFN Exposed Pad

6373

32-UFQFN Exposed Pad

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LCMXO2-1200HC-6TG144CR1

MachXO2 Field Programmable Gate Array (FPGA) IC 107 65536 1280 144-LQFP

8190

144-LQFP

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LCMXO2-1200HC-5TG144CR1

MachXO2 Field Programmable Gate Array (FPGA) IC 107 65536 1280 144-LQFP

2576

144-LQFP

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LCMXO2-1200HC-5TG100CR1

MachXO2 Field Programmable Gate Array (FPGA) IC 79 65536 1280 100-LQFP

6467

100-LQFP

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LCMXO2-1200HC-6MG132IR1

MachXO2 Field Programmable Gate Array (FPGA) IC 104 65536 1280 132-LFBGA, CSPBGA

7720

132-LFBGA, CSPBGA

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LCMXO2-1200HC-6TG100IR1

MachXO2 Field Programmable Gate Array (FPGA) IC 79 65536 1280 100-LQFP

2267

100-LQFP

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LCMXO2-1200HC-5TG144IR1

MachXO2 Field Programmable Gate Array (FPGA) IC 107 65536 1280 144-LQFP

3613

144-LQFP

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LCMXO2-256ZE-3SG32C

MachXO2 Field Programmable Gate Array (FPGA) IC 21 256 32-UFQFN Exposed Pad

7294

32-UFQFN Exposed Pad

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LCMXO2-256ZE-2SG32C

MachXO2 Field Programmable Gate Array (FPGA) IC 21 256 32-UFQFN Exposed Pad

7635

32-UFQFN Exposed Pad

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LCMXO2-256ZE-2SG32I

MachXO2 Field Programmable Gate Array (FPGA) IC 21 256 32-UFQFN Exposed Pad

3589

32-UFQFN Exposed Pad

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LCMXO2-256ZE-1SG32I

MachXO2 Field Programmable Gate Array (FPGA) IC 21 256 32-UFQFN Exposed Pad

4645

32-UFQFN Exposed Pad

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LCMXO2-1200ZE-3TG144CR1

MachXO2 Field Programmable Gate Array (FPGA) IC 107 65536 1280 144-LQFP

1047

144-LQFP

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