National Semiconductor

EE PLD, 25NS, PAL-TYPE

General Description

The EECMOS GAL20V8QS devices are fabricated using National's CS80BEV 0.8μ Electrically Erasable CMOS pro-cess.

This advanced process makes National's GAL20V8QS extremely fast, allowing controlled output edge rates which dramatically

reduce noise. Low noise is actually specified and guaranteed with National's GAL20V8QS Quiet Series™ devices.

National's fast programming algorithm allows the GAL20V8QS to be programmed significantly faster than similar devices using

industry standard programmers. Fast programming reduces the cost of programming by greatly increasing programming throughput.

National guarantees a minimum of 100 erase/write cycles.

Unique test circuitry and reprogrammable cells allow com-plete AC, DC, cell, and functionality testing during manufac-ture.

Therefore, National guarantees 100% field programm-ability and functionality of GAL® devices. In addition, a se-curity

circuit is built-in,providing proprietary designs with copy protection.

Features

• High performance 0.8 μ EECMOS technology

     -10 ns maximum propagation delay

     - 5 ns setup time delay

     - 7.5 ns clock to registered output delay

     - fMAx =80 MHz

     - Reduced ground bounce

     -2000V ESD protection

• Reduced power

     - lcc max = 90 mA @ 25 MHz

• Electrically erasable cell technology

     -100% tested at manufacture

• Fast programming algorithm

     -Reduces programming cost, increases throughput

• Emulates popular PAL® devices

• Fully supported by National's OPAL™ and OPAL jr software as well as 3rd-party PLD development software

• Commercial and industrial grades

How to choose FPGA for your project?

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