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12V1 HCS12 Microcontroller IC 16-Bit 25MHz 128KB (128K x 8) FLASH 100-LQFP (14x14)

Introduction

The MC9S12G-Family is an optimized, automotive, 16-bit microcontroller product line focused on

low-cost, high-performance, and low pin-count. This family is intended to bridge between high-end 8-bit

microcontrollers and high-performance 16-bit microcontrollers, such as the MC9S12XS-Family. The

MC9S12G-Family is targeted at generic automotive applications requiring CAN or LIN/J2602

communication. Typical examples of these applications include body controllers, occupant detection, door

modules, seat controllers, RKE receivers, smart actuators, lighting modules, and smart junction boxes.

The MC9S12G-Family uses many of the same features found on the MC9S12XS- and MC9S12P-Family,

including error correction code (ECC) on flash memory, a fast analog-to-digital converter (ADC) and a

frequency modulated phase locked loop (IPLL) that improves the EMC performance. 

The MC9S12G-Family is optimized for lower program memory sizes down to 16k. In order to simplify

customer use it features an EEPROM with a small 4 bytes erase sector size.

The MC9S12G-Family deliver all the advantages and efficiencies of a 16-bit MCU while retaining the low

cost, power consumption, EMC, and code-size efficiency advantages currently enjoyed by users of NXP’s

existing 8-bit and 16-bit MCU families. Like the MC9S12XS-Family, the MC9S12G-Family run 16-bit

wide accesses without wait states for all peripherals and memories. The MC9S12G-Family is available in

100-pin LQFP, 64-pin LQFP, 48-pin LQFP/QFN, 32-pin LQFP and 20-pin TSSOP package options and

aims to maximize the amount of functionality especially for the lower pin count packages. In addition to

the I/O ports available in each module, further I/O ports are available with interrupt capability allowing

wake-up from stop or wait modes.

Chip-Level Features

On-chip modules available within the family include the following features:

• S12 CPU core

• Up to 240 Kbyte on-chip flash with ECC

• Up to 4 Kbyte EEPROM with ECC

• Up to 11 Kbyte on-chip SRAM

• Phase locked loop (IPLL) frequency multiplier with internal filter

• 4–16 MHz amplitude controlled Pierce oscillator

• 1 MHz internal RC oscillator

• Timer module (TIM) supporting up to eight channels that provide a range of 16-bit input capture,

output compare, counter, and pulse accumulator functions

• Pulse width modulation (PWM) module with up to eight x 8-bit channels

• Up to 16-channel, 10 or 12-bit resolution successive approximation analog-to-digital converter

(ADC)

• Up to two 8-bit digital-to-analog converters (DAC)

• Up to one 5V analog comparator (ACMP)

• Up to three serial peripheral interface (SPI) modules

• Up to three serial communication interface (SCI) modules supporting LIN communications

• Up to one multi-scalable controller area network (MSCAN) module (supporting CAN protocol

2.0A/B)

• On-chip voltage regulator (VREG) for regulation of input supply and all internal voltages

• Autonomous periodic interrupt (API)

• Precision fixed voltage reference for ADC conversions

• Optional reference voltage attenuator module to increase ADC accuracy

56800E 56F8xxx Microcontroller IC 16-Bit 32MHz 12KB (6K x 16) FLASH 32-LQFP (7x7)

56F8013/56F8011 Description

The 56F8013/56F8011 is a member of the 56800E core-based family of Digital Signal Controllers (DSCs).

It combines, on a single chip, the processing power of a DSP and the functionality of a microcontroller

with a flexible set of peripherals to create an extremely cost-effective solution. Because of its low cost,

configuration flexibility, and compact program code, the 56F8013/56F8011 is well-suited for many

applications. The 56F8013/56F8011 includes many peripherals that are especially useful for industrial

control, motion control, home appliances, general purpose inverters, smart sensors, fire and security

systems, switched mode power supply, power management, and medical monitoring applications.

The 56800E core is based on a dual Harvard-style architecture consisting of three execution units

operating in parallel, allowing as many as six operations per instruction cycle. The MCU-style

programming model and optimized instruction set allow straightforward generation of efficient, compact

DSP and control code. The instruction set is also highly efficient for C compilers to enable rapid

development of optimized control applications.

The 56F8013/56F8011 supports program execution from internal memories. Two data operands can be

accessed from the on-chip data RAM per instruction cycle. The 56F8013/56F8011 also offers up to 26

General Purpose Input/Output (GPIO) lines, depending on peripheral configuration.

The 56F8013 Digital Signal Controller includes 16KB of Program Flash and 4KB of Unified

Data/Program RAM. The 56F8011 Digital Signal Controller includes 12KB of Program Flash and 2KB

of Unified Data/Program RAM. Program Flash memory can be independently bulk erased or erased in

pages. Program Flash page erase size is 512 Bytes (256 Words).

A full set of programmable peripherals—PWM, ADCs, SCI, SPI, I2C, Quad Timer—supports various

applications. Each peripheral can be independently shut down to save power. Any pin in these peripherals

can also be used as General Purpose Input/Outputs (GPIOs).

56F8013/56F8011 Features

Digital Signal Controller Core

• Efficient 16-bit 56800E family Digital Signal Controller (DSC) engine with dual Harvard architecture

• As many as 32 Million Instructions Per Second (MIPS) at 32MHz core frequency

• Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC)

• Four 36-bit accumulators, including extension bits

• 32-bit arithmetic and logic multi-bit shifter

• Parallel instruction set with unique DSP addressing modes

• Hardware DO and REP loops

• Three internal address buses

• Four internal data buses

• Instruction set supports both DSP and controller functions

• Controller-style addressing modes and instructions for compact code

• Efficient C compiler and local variable support

• Software subroutine and interrupt stack with depth limited only by memory

• JTAG/Enhanced On-Chip Emulation (OnCE) for unobtrusive, processor speed-independent, real-time

debugging

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CPU12 HC12 Microcontroller IC 16-Bit 8MHz 60KB (60K x 8) FLASH 112-LQFP (20x20)

Introduction

The MC68HC912D60A microcontroller unit (MCU) is a 16-bit device

available in two package options, 80-pin QFP and 112-pin TQFP. Onchip

peripherals include a 16-bit central processing unit (CPU12), 60K

bytes of flash EEPROM, 2K bytes of RAM, 1K bytes of EEPROM, two

asynchronous serial communication interfaces (SCI), a serial peripheral

interface (SPI), an enhanced capture timer (ECT), two (one on 80QFP)

8-channel,10-bit analog-to-digital converters (ATD), a four-channel

pulse-width modulator (PWM), and a CAN 2.0 A, B software compatible

module (MSCAN12). System resource mapping, clock generation,

interrupt control and bus interfacing are managed by the lite integration

module (LIM). The MC68HC912D60A has full 16-bit data paths

throughout, however, the external bus can operate in an 8-bit narrow

mode so single 8-bit wide memory can be interfaced for lower cost

systems. The inclusion of a PLL circuit allows power consumption and

performance to be adjusted to suit operational requirements. In addition

to the I/O ports available in each module, 16 (2 on 80QFP) I/O port pins

are available with Key-Wake-Up capability from STOP or WAIT mode.

Features

• 16-bit CPU12

– Upward compatible with M68HC11 instruction set

– Interrupt stacking and programmer’s model identical to

M68HC11

– 20-bit ALU

– Instruction queue

– Enhanced indexed addressing

• Multiplexed bus

– Single chip or expanded

– 16 address/16 data wide or 16 address/8 data narrow mode

• Two 8-bit ports with key wake-up interrupt (2 pins only are

available on 80QFP) and one I2C start bit detector (112TQFP

only)

• Memory

– 60K byte flash EEPROM, made of a 28K module and a 32K

module with 8K bytes protected BOOT section in each module

(MC68HC912D60A)

– 1K byte EEPROM

– 2K byte RAM

• Analog-to-digital converters

– 2 x 8-channels, 10-bit resolution in 112TQFP

– 1 x 8-channels, 8-bit resolution in 80QFP

• 1M bit per second, CAN 2.0 A, B software compatible module

– Two receive and three transmit buffers

– Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit or

8 x 8 bit

– Four separate interrupt channels for Rx, Tx, error and wake-up

– Low-pass filter wake-up function

– In 80QFP, only TxCAN and RxCAN pins are available

– Loop-back for self test operation

– Programmable link to a timer input capture channel, for timestamping

and network synchronization.

• Enhanced capture timer (ECT)

– 16-bit main counter with 7-bit prescaler

– 8 programmable input capture or output compare channels; 4

of the 8 input captures with buffer

– Input capture filters and buffers, three successive captures on

four channels, or two captures on four channels with a

capture/compare selectable on the remaining four

– Four 8-bit or two 16-bit pulse accumulators

– 16-bit modulus down-counter with 4-bit prescaler

– Four user-selectable delay counters for signal filtering

• 4 PWM channels with programmable period and duty cycle

– 8-bit 4-channel or 16-bit 2-channel

– Separate control for each pulse width and duty cycle

– Center- or left-aligned outputs

– Programmable clock select logic with a wide range of

frequencies

• Serial interfaces

– Two asynchronous serial communications interfaces (SCI)

– MI-Bus implemented on final devices

– Synchronous serial peripheral interface (SPI)

• LIM (light integration module)

– WCR (windowed COP watchdog, real time interrupt, clock

monitor)

– ROC (reset and clocks)

– MEBI (multiplexed external bus interface)

– MBI (internal bus interface and map)

– INT (interrupt control)

• Clock generation

– Phase-locked loop clock frequency multiplier

– Limp home mode in absence of external clock

– Slow mode divider

– Low power 0.5 to 16 MHz crystal oscillator reference clock

– Option of a Pierce or Colpitts oscillator

• 112-Pin TQFP package or 80-pin QFP package

– Up to 68 general-purpose I/O lines, plus up to 18 input-only

lines in 112TQFP

or

Up to 48 general-purpose I/O lines, plus up to 10 input-only

lines in 80QFP

• 8MHz operation at 5V

• Development support

– Single-wire background debug™ mode (BDM)

– On-chip hardware breakpoints

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