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HCS12 HCS12 Microcontroller IC 16-Bit 25MHz 256KB (256K x 8) FLASH 80-QFP (14x14)

MC9S12DT256

Covers also

MC9S12A256, MC9S12DJ256

MC9S12DG256

Overview

The MC9S12DT256 microcontroller unit (MCU) is a 16-bit device composed of standard on-chip

peripherals including a 16-bit central processing unit (HCS12 CPU), 256K bytes of Flash EEPROM, 12K

bytes of RAM, 4K bytes of EEPROM, two asynchronous serial communications interfaces (SCI), three

serial peripheral interfaces (SPI), an 8-channel IC/OC enhanced capture timer, two 8-channel, 10-bit

analog-to-digital converters (ADC), an 8-channel pulse-width modulator (PWM), a digital Byte Data Link

Controller (BDLC), 29 discrete digital I/O channels (Port A, Port B, Port K and Port E), 20 discrete digital

I/O lines with interrupt and wakeup capability, three CAN 2.0 A, B software compatible modules

(MSCAN12), and an Inter-IC Bus. The MC9S12DT256 has full 16-bit data paths throughout. However,

the external bus can operate in an 8-bit narrow mode so single 8-bit wide memory can be interfaced for

lower cost systems. The inclusion of a PLL circuit allows power consumption and performance to be

adjusted to suit operational requirements.

Features

• HCS12 Core

– 16-bit HCS12 CPU

i. Upward compatible with M68HC11 instruction set

ii. Interrupt stacking and programmer’s model identical to M68HC11

iii.Instruction queue

iv. Enhanced indexed addressing

– MEBI (Multiplexed External Bus Interface)

– MMC (Module Mapping Control)

– INT (Interrupt control)

– BKP (Breakpoints)

– BDM (Background Debug Mode)

• CRG

– Low current Colpitts or Pierce oscillator

– PLL

– COP watchdog

– Real time interrupt

– Clock Monitor

• 8-bit and 4-bit ports with interrupt functionality

– Digital filtering

– Programmable rising or falling edge trigger

• Memory

– 256K Flash EEPROM

– 4K byte EEPROM

– 12K byte RAM

• Two 8-channel Analog-to-Digital Converters

– 10-bit resolution

– External conversion trigger capability

• Three 1M bit per second, CAN 2.0 A, B software compatible modules

– Five receive and three transmit buffers

– Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit or 8 x 8 bit

– Four separate interrupt channels for Rx, Tx, error and wake-up

– Low-pass filter wake-up function

– Loop-back for self test operation

• Enhanced Capture Timer

– 16-bit main counter with 7-bit prescaler

– 8 programmable input capture or output compare channels

– Four 8-bit or two 16-bit pulse accumulators

• 8 PWM channels

– Programmable period and duty cycle

– 8-bit 8-channel or 16-bit 4-channel

– Separate control for each pulse width and duty cycle

– Center-aligned or left-aligned outputs

– Programmable clock select logic with a wide range of frequencies

– Fast emergency shutdown input

– Usable as interrupt inputs

• Serial interfaces

– Two asynchronous Serial Communications Interfaces (SCI)

– Three Synchronous Serial Peripheral Interface (SPI)

• Byte Data Link Controller (BDLC)

– SAE J1850 Class B Data Communications Network Interface Compatible and ISO Compatible

for Low-Speed (<125 Kbps) Serial Data Communications in Automotive Applications

• Inter-IC Bus (IIC)

– Compatible with I2C Bus standard

– Multi-master operation

– Software programmable for one of 256 different serial clock frequencies

• 112-Pin LQFP package

– I/O lines with 5V input and drive capability

– 5V A/D converter inputs

– Operation at 50MHz equivalent to 25MHz Bus Speed

– Development support

– Single-wire background debug™ mode (BDM)

– On-chip hardware breakpoints

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56800E 56F8xxx Microcontroller IC 16-Bit 60MHz 32KB (16K x 16) FLASH 64-LQFP (10x10)

Device Description

The 56F8323 and 56F8123 are members of the 56800E core-based family of controllers. Each combines,

on a single chip, the processing power of a Digital Signal Processor (DSP) and the functionality of a

microcontroller with a flexible set of peripherals to create an extremely cost-effective solution. Because

of their low cost, configuration flexibility, and compact program code, the 56F8323 and 56F8123 are

well-suited for many applications. The devices include many peripherals that are especially useful for

automotive control (56F8323 only); industrial control and networking; motion control; home appliances;

general purpose inverters; smart sensors; fire and security systems; power management; and medical

monitoring applications.

The 56800E core is based on a Harvard-style architecture consisting of three execution units operating in

parallel, allowing as many as six operations per instruction cycle. The MCU-style programming model

and optimized instruction set allow straightforward generation of efficient, compact DSP and control

code. The instruction set is also highly efficient for C Compilers to enable rapid development of

optimized control applications.

The 56F8323 and 56F8123 support program execution from internal memories. Two data operands can be

accessed from the on-chip data RAM per instruction cycle. These devices also provide one external

dedicated interrupt line and up to 27 General Purpose Input/Output (GPIO) lines, depending on peripheral

configuration.

56F8323 Features

The 56F8323 controller includes 32KB of Program Flash and 8KB of Data Flash, each programmable

through the JTAG port, with 4KB of Program RAM and 8KB of Data RAM. A total of 8KB of Boot Flash

is incorporated for easy customer inclusion of field-programmable software routines that can be used to

program the main Program and Data Flash memory areas. Both Program and Data Flash memories can be

independently bulk erased or erased in pages. Program Flash page erase size is 1KB. Boot and Data Flash

page erase size is 512 bytes. The Boot Flash memory can also be either bulk or page erased.

A key application-specific feature of the 56F8323 is the inclusion of one Pulse Width Modulator (PWM)

module. This module incorporates three complementary, individually programmable PWM signal output

pairs and is also capable of supporting six independent PWM functions to enhance motor control

functionality. Complementary operation permits programmable dead time insertion, distortion correction

via current sensing by software, and separate top and bottom output polarity control. The up-counter value

is programmable to support a continuously variable PWM frequency. Edge-aligned and center-aligned

synchronous pulse width control (0% to 100% modulation) is supported. The device is capable of

controlling most motor types: ACIM (AC Induction Motors); both BDC and BLDC (Brush and Brushless

DC motors); SRM and VRM (Switched and Variable Reluctance Motors); and stepper motors. The PWM

incorporates fault protection and cycle-by-cycle current limiting with sufficient output drive capability to

directly drive standard optoisolators. A “smoke-inhibit”, write-once protection feature for key parameters

is also included. A patented PWM waveform distortion correction circuit is also provided. Each PWM is

double-buffered and includes interrupt controls to permit integral reload rates to be programmable from

1/2 (center-aligned mode only) to 16. The PWM module provides reference outputs to synchronize the

Analog-to-Digital Converters (ADCs) through Quad Timer C, Channel 2.

The 56F8323 incorporates one Quadrature Decoder capable of capturing all four transitions on the

two-phase inputs, permitting generation of a number proportional to actual position. Speed computation

capabilities accommodate both fast- and slow-moving shafts. An integrated watchdog timer in the

Quadrature Decoder can be programmed with a time-out value to alarm when no shaft motion is detected.

Each input is filtered to ensure only true transitions are recorded.

This controller also provides a full set of standard programmable peripherals that include two Serial

Communications Interfaces (SCIs), two Serial Peripheral Interfaces (SPIs), two Quad Timers, and

FlexCAN. Any of these interfaces can be used as General Purpose Input/Outputs (GPIOs) if that function

is not required. A Flex Controller Area Network (FlexCAN) interface (CAN Version 2.0 B-compliant) and

an internal interrupt controller are also a part of the 56F8323.

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HCS12X HCS12X Microcontroller IC 16-Bit 50MHz 128KB (128K x 8) FLASH 80-QFP (14x14)

MC9S12XEP100

Covers MC9S12XE Family

Introduction

The MC9S12XE-Family of micro controllers is a further development of the S12XD-Family including

new features for enhanced system integrity and greater functionality. These new features include a

Memory Protection Unit (MPU) and Error Correction Code (ECC) on the Flash memory together with

enhanced EEPROM functionality (EEE), an enhanced XGATE, an Internally filtered, frequency

modulated Phase Locked Loop (IPLL) and an enhanced ATD. The E-Family extends the S12X product

range up to 1MB of Flash memory with increased I/O capability in the 208-pin version of the flagship

MC9S12XE100.

The MC9S12XE-Family delivers 32-bit performance with all the advantages and efficiencies of a 16 bit

MCU. It retains the low cost, power consumption, EMC and code-size efficiency advantages currently

enjoyed by users of Freescale’s existing 16-Bit MC9S12 and S12X MCU families. There is a high level of

compatibility between the S12XE and S12XD families.

The MC9S12XE-Family features an enhanced version of the performance-boosting XGATE co-processor

which is programmable in “C” language and runs at twice the bus frequency of the S12X with an

instruction set optimized for data movement, logic and bit manipulation instructions and which can service

any peripheral module on the device. The new enhanced version has improved interrupt handling

capability and is fully compatible with the existing XGATE module.

The MC9S12XE-Family is composed of standard on-chip peripherals including up to 64Kbytes of RAM,

eight asynchronous serial communications interfaces (SCI), three serial peripheral interfaces (SPI), an 8-

channel IC/OC enhanced capture timer (ECT), two 16-channel, 12-bit analog-to-digital converters, an 8-

channel pulse-width modulator (PWM), five CAN 2.0 A, B software compatible modules (MSCAN12),

two inter-IC bus blocks (IIC), an 8-channel 24-bit periodic interrupt timer (PIT) and an 8-channel 16-bit

standard timer module (TIM).

The MC9S12XE-Family uses 16-bit wide accesses without wait states for all peripherals and memories.

The non-multiplexed expanded bus interface available on the 144/208-Pin versions allows an easy

interface to external memories.

In addition to the I/O ports available in each module, up to 26 further I/O ports are available with interrupt

capability allowing Wake-Up from STOP or WAIT modes. The MC9S12XE-Family is available in 208-

Pin MAPBGA, 144-Pin LQFP, 112-Pin LQFP or 80-Pin QFP options.

Features

• 16-Bit CPU12X

— Upward compatible with MC9S12 instruction set with the exception of five Fuzzy instructions

(MEM, WAV, WAVR, REV, REVW) which have been removed

— Enhanced indexed addressing

— Access to large data segments independent of PPAGE

• INT (interrupt module)

— Eight levels of nested interrupts

— Flexible assignment of interrupt sources to each interrupt level.

— External non-maskable high priority interrupt (XIRQ)

— Internal non-maskable high priority Memory Protection Unit interrupt

— Up to 24 pins on ports J, H and P configurable as rising or falling edge sensitive interrupts

• EBI (external bus interface)(available in 208-Pin and 144-Pin packages only)

— Up to four chip select outputs to select 16K, 1M, 2M and up to 4MByte address spaces

— Each chip select output can be configured to complete transaction on either the time-out of one

of the two wait state generators or the deassertion of EWAIT signal

• MMC (module mapping control)

• DBG (debug module)

— Monitoring of CPU and/or XGATE busses with tag-type or force-type breakpoint requests

— 64 x 64-bit circular trace buffer captures change-of-flow or memory access information

• BDM (background debug mode)

• MPU (memory protection unit)

— 8 address regions definable per active program task

— Address range granularity as low as 8-bytes

— No write / No execute Protection Attributes

— Non-maskable interrupt on access violation

• XGATE

— Programmable, high performance I/O coprocessor module

— Transfers data to or from all peripherals and RAM without CPU intervention or CPU wait states

— Performs logical, shifts, arithmetic, and bit operations on data

— Can interrupt the HCS12X CPU signalling transfer completion

— Triggers from any hardware module as well as from the CPU possible

— Two interrupt levels to service high priority tasks

— Hardware support for stack pointer initialisation

• OSC_LCP (oscillator)

— Low power loop control Pierce oscillator utilizing a 4MHz to 16MHz crystal

— Good noise immunity

— Full-swing Pierce option utilizing a 2MHz to 40MHz crystal

— Transconductance sized for optimum start-up margin for typical crystals

• IPLL (Internally filtered, frequency modulated phase-locked-loop clock generation)

— No external components required

— Configurable option to spread spectrum for reduced EMC radiation (frequency modulation)

• CRG (clock and reset generation)

— COP watchdog

— Real time interrupt

— Clock monitor

— Fast wake up from STOP in self clock mode

• Memory Options

— 128K, 256k, 384K, 512K, 768K and 1M byte Flash

— 2K, 4K byte emulated EEPROM

— 12K, 16K, 24K, 32K, 48K and 64K Byte RAM

• Flash General Features

— 64 data bits plus 8 syndrome ECC (Error Correction Code) bits allow single bit failure

correction and double fault detection

— Erase sector size 1024 bytes

— Automated program and erase algorithm

• D-Flash Features

— Up to 32 Kbytes of D-Flash memory with 256 byte sectors for user access.

— Dedicated commands to control access to the D-Flash memory over EEE operation.

— Single bit fault correction and double bit fault detection within a word during read operations.

— Automated program and erase algorithm with verify and generation of ECC parity bits.

— Fast sector erase and word program operation.

— Ability to program up to four words in a burst sequence

• Emulated EEPROM Features

— Automatic EEE file handling using an internal Memory Controller.

— Automatic transfer of valid EEE data from D-Flash memory to buffer RAM on reset.

— Ability to monitor the number of outstanding EEE related buffer RAM words left to be

programmed into D-Flash memory.

— Ability to disable EEE operation and allow priority access to the D-Flash memory.

— Ability to cancel all pending EEE operations and allow priority access to the D-Flash memory.

• Two 16-channel, 12-bit Analog-to-Digital Converters

— 8/10/12 Bit resolution

— 3µs, 10-bit single conversion time

— Left/right, signed/unsigned result data

— External and internal conversion trigger capability

— Internal oscillator for conversion in Stop modes

— Wake from low power modes on analog comparison > or <= match

• Five MSCAN (1 M bit per second, CAN 2.0 A, B software compatible modules)

— Five receive and three transmit buffers

— Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit, or 8 x 8 bit

— Four separate interrupt channels for Rx, Tx, error, and wake-up

— Low-pass filter wake-up function

— Loop-back for self-test operation

• ECT (enhanced capture timer)

— 8 x 16-bit channels for input capture or output compare

— 16-bit free-running counter with 8-bit precision prescaler

— 16-bit modulus down counter with 8-bit precision prescaler

— Four 8-bit or two 16-bit pulse accumulators

• TIM (standard timer module)

— 8 x 16-bit channels for input capture or output compare

— 16-bit free-running counter with 8-bit precision prescaler

— 1 x 16-bit pulse accumulator

• PIT (periodic interrupt timer)

— Up to eight timers with independent time-out periods

— Time-out periods selectable between 1 and 224 bus clock cycles

— Time-out interrupt and peripheral triggers

• 8 PWM (pulse-width modulator) channels

— 8 channel x 8-bit or 4 channel x 16-bit Pulse Width Modulator

— programmable period and duty cycle per channel

— Center- or left-aligned outputs

— Programmable clock select logic with a wide range of frequencies

— Fast emergency shutdown input

• Three Serial Peripheral Interface Modules (SPI)

— Configurable for 8 or 16-bit data size

• Eight Serial Communication Interfaces (SCI)

— Standard mark/space non-return-to-zero (NRZ) format

— Selectable IrDA 1.4 return-to-zero-inverted (RZI) format with programmable pulse widths

• Two Inter-IC bus (IIC) Modules

— Multi-master operation

— Software programmable for one of 256 different serial clock frequencies

— Broadcast mode support

— 10-bit address support

• On-Chip Voltage Regulator

— Two parallel, linear voltage regulators with bandgap reference

— Low-voltage detect (LVD) with low-voltage interrupt (LVI)

— Power-on reset (POR) circuit

— 3.3V and 5V range operation

— Low-voltage reset (LVR)

• Low-power wake-up timer (API)

— Available in all modes including Full Stop Mode

— Trimmable to +-5% accuracy

— Time-out periods range from 0.2ms to ~13s with a 0.2ms resolution

• Input/Output

— Up to 152 general-purpose input/output (I/O) pins plus 2 input-only pins

— Hysteresis and configurable pull up/pull down device on all input pins

— Configurable drive strength on all output pins

• Package Options

— 208-pin MAPBGA

— 144-pin low-profile quad flat-pack (LQFP)

— 112-pin low-profile quad flat-pack (LQFP)

— 80-pin quad flat-pack (QFP)

• 50MHz maximum CPU bus frequency, 100MHz maximum XGATE bus frequency

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