National Semiconductor

EE PLD, 25NS, PAL-TYPE PQCC28

General Description

The EECMOS GAL20V8QSdevices are fabricated using National's CS80BEV 0.8μ Electrically Erasable CMOS pro-cess.

This advanced process makes National's GAL20V8QSextremely fast, allowing controlled output edge rates which

dramatically reduce noise. Low noise is actually specified and guaranteed with National's GAL20V8QS Quiet

SeriesTM devices.

National's fast programming algorithm allows the GAL20V8QS to be programmed significantly faster than similar devices using 

industry standard programmers. Fast programming reduces the cost of programming by greatly increasing programming throughput. 

National guarantees a minimum of 100 erase/write cycles.

Unique test circuitry and reprogrammable cells allow com-plete AC, DC, cell, and functionality testing during manufac-ture. 

Therefore, National guarantees 100% field programm-ability and functionality of GAL®devices. In addition, a se-curity circuit

is built-in, providing proprietary designs with copy protection.

Features

• High performance 0.8μ EECMOS technology
  

     -10 ns maximum propagation delay

     - 5 ns setup time delay

     - 7.5 ns clock to registered output delay

     - fMAx 80 MHz

     - Reduced ground bounce

     -2000V ESD protection

• Reduced power
  

     - lcc max =90 mA @ 25 MHz

• Electrically erasable cell technology
  

     -100% tested at manufacture

• Fast programming algorithm
  

     - Reduces programming cost, increases throughput

• Emulates popular PAL® devices

• Fully supported by National's OPALTM and OPAL jr software as well as 3rd-party PLD development software
  

• Commercial and industrial grades

How to choose FPGA for your project?

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IC CPLD 8MC 15NS 20PLCC

General Description

The EECMOS GAL16V8QS devices are fabricated using National's CS80BEV 0.8μ Electrically Erasable CMOS pro-cess.

This advanced process makes National's GAL16V8QS extremely fast, allowing controlled output edge rates which dramatically

reduce noise. Low noise is actually specified and guaranteed with National's GAL16V8QS Quiet Series™ devices.

National's fast programming algorithm allows the GAL16V8QS to be programmed significantly faster than similar devices using

industry standard programmers. Fast programming reduces the cost of programming by greatly increasing programming throughput.

National guarantees a minimum of 100 erase/write cycles.

Unique test circuitry and reprogrammable cells allow com-plete AC, DC, cell, and functionality testing during manufac-ture.

Therefore, National guarantees 100% field programm-ability and functionality of GAL® devices. In addition, a se-curity

circuit is built-in,providing proprietary designs with copy protection.

Features

• High performance 0.8 μ EECMOS technology

     -10 ns maximum propagation delay

     - 5 ns setup time delay

     - 7.5 ns clock to registered output delay

     - fMAx =80 MHz

     - Reduced ground bounce

     -2000V ESD protection

• Reduced power

     - lcc max = 90 mA @ 25 MHz

• Electrically erasable cell technology

     -100% tested at manufacture

• Fast programming algorithm

     -Reduces programming cost, increases throughput

• Emulates popular PAL® devices

• Fully supported by National's OPAL™ and OPAL jr software as well as 3rd-party PLD development software

• Commercial and industrial grades

How to choose FPGA for your project?

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GAL20V8QS-10L Programmable Logic Device (PLD) IC 8 Macrocells 28-PLCC (11.43x11.43)

General Description

The EECMOS GAL20V8QS devices are fabricated using National's CS80BEV 0.8μ Electrically Erasable CMOS pro-cess.

This advanced process makes National's GAL20V8QS extremely fast, allowing controlled output edge rates which dramatically

reduce noise. Low noise is actually specified and guaranteed with National's GAL20V8QS Quiet Series™ devices.

National's fast programming algorithm allows the GAL20V8QS to be programmed significantly faster than similar devices using

industry standard programmers. Fast programming reduces the cost of programming by greatly increasing programming throughput.

National guarantees a minimum of 100 erase/write cycles.

Unique test circuitry and reprogrammable cells allow com-plete AC, DC, cell, and functionality testing during manufac-ture.

Therefore, National guarantees 100% field programm-ability and functionality of GAL® devices. In addition, a se-curity

circuit is built-in,providing proprietary designs with copy protection.

Features

• High performance 0.8 μ EECMOS technology

     -10 ns maximum propagation delay

     - 5 ns setup time delay

     - 7.5 ns clock to registered output delay

     - fMAx =80 MHz

     - Reduced ground bounce

     -2000V ESD protection

• Reduced power

     - lcc max = 90 mA @ 25 MHz

• Electrically erasable cell technology

     -100% tested at manufacture

• Fast programming algorithm

     -Reduces programming cost, increases throughput

• Emulates popular PAL® devices

• Fully supported by National's OPAL™ and OPAL jr software as well as 3rd-party PLD development software

• Commercial and industrial grades

How to choose FPGA for your project?

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LOW VOLTAGE E2CMOS PLD GENERIC A

General Description

The NSC E²CMOS™ GAL人® devices combine a high per-formance CMOS process with electrically erasable floating

gate technology. This programmable memory technology applied to array logic provides designers with reconfigurable

logic and bipolar performance at significantly reduced pow-er levels.

The 24-pin GAL22V10 features 22 inputs, and 10 program-mable Output Logic Macro Cells (OLMCs) allowing each

TRI-STATE® output to be configured by the user. The archi-tecture of each output is user-programmable for registered

or combinatorial operation, active high or low polarity, and as an input, output or bidirectional I/O. This architecture

features variable product term distribution, from 8 to 16 logi-cal product terms to each output, as shown in the logic dia-

gram. CMOS circuitry allows the GAL22V10 to consume just 90 mA typical lcc which represents a 50% saving in power

when compared to its bipolar counterparts. Synchronous preset and asynchronous reset product terms have been

added which are common to all output registers to enhance system operation. The GAL22V10 is directly compatible

with the bipolar PAL22V10 in terms of functionality, fuse map, pinout, and electrical characteristics.

Programming is accomplished using industry standard avail-able hardware and software tools. NSC guarantees a mini-

mum 100 erase/write cycles.

Unique test circuitry and reprogrammable cells allow com-plete AC, DC, cell and functionality testing during manufac-

ture. Therefore, NSC guarantees 100% field programmabili-ty of all GAL devices. In addition, electronic signature is

available to provide positive device ID. A security circuit isbuilt-in, providing proprietary designs with copy protection.

Features

• High performance E²CMOS technology

     -15 ns maximum propagation delay

     -fmax = 45 MHz with feedback

     -TTL compatible 16 mA outputs

     -UltraMOS® Ill advanced CMOS technology

     -Internal pull-up resistor on all pins

• Electrically erasable cell technology

     -Reconfigurable logic

     -Reprogrammable cells

     -100% tested/guaranteed 100% yields

     -High speed electrical erasure(<50 ms)

     -20 year data retention

• Ten output logic macrocells

     -Maximum Flexibility

     -Programmable output polarity

     -Maximum flexibility for complex logic designs

     -Full function/fuse map/parametric compatibility with PAL22V10 devices

• Variable product term distribution

     -From 8 to 16 product terms per output data function

• Globai synchronous preset and asynchronous reset

• Preload and power-up reset of all registers

     -100% functional testability

• Fully supported by National OPAL™ and OPALjr development software

• Security cell prevents copying logic

How to choose FPGA for your project?