NXP USA Inc.

HCS12 HCS12 Microcontroller IC 16-Bit 25MHz 32KB (32K x 8) FLASH 80-QFP (14x14)

Introduction

The MC9S12C-Family / MC9S12GC-Family are 48/52/80 pin Flash-based MCU families, which deliver

the power and flexibility of the 16-bit core to a whole new range of cost and space sensitive, general

purpose industrial and automotive network applications. All MC9S12C-Family / MC9S12GC-Family

members feature standard on-chip peripherals including a 16-bit central processing unit (CPU12), up to

128K bytes of Flash EEPROM, up to 4K bytes of RAM, an asynchronous serial communications interface

(SCI), a serial peripheral interface (SPI), an 8-channel 16-bit timer module (TIM), a 6-channel 8-bit pulse

width modulator (PWM), an 8-channel, 10-bit analog-to-digital converter (ADC).

The MC9S12C128-Family members also feature a CAN 2.0 A, B software compatible module

(MSCAN12).

All MC9S12C-Family / MC9S12GC-Family devices feature full 16-bit data paths throughout. The

inclusion of a PLL circuit allows power consumption and performance to be adjusted to suit operational

requirements. In addition to the I/O ports available in each module, up to 10 dedicated I/O port bits are

available with wake-up capability from stop or wait mode. The devices are available in 48-, 52-, and 80-

pin QFP packages, with the 80-pin version pin compatible to the HCS12 A, B, and D Family derivatives.

Features

• 16-bit HCS12 core:

— HCS12 CPU

– Upward compatible with M68HC11 instruction set

– Interrupt stacking and programmer’s model identical to M68HC11

– Instruction queue

– Enhanced indexed addressing

— MMC (memory map and interface)

— INT (interrupt control)

— BDM (background debug mode)

— DBG12 (enhanced debug12 module, including breakpoints and change-of-flow trace buffer)

— MEBI (multiplexed expansion bus interface) available only in 80-pin package version

• Wake-up interrupt inputs:

— Up to 12 port bits available for wake up interrupt function with digital filtering

• Memory options:

— 16K or 32Kbyte Flash EEPROM (erasable in 512-byte sectors)

64K, 96K, or 128Kbyte Flash EEPROM (erasable in 1024-byte sectors)

— 1K, 2K or 4K Byte RAM

• Analog-to-digital converters:

— One 8-channel module with 10-bit resolution

— External conversion trigger capability

• Available on MC9S12C Family:

— One 1M bit per second, CAN 2.0 A, B software compatible module

— Five receive and three transmit buffers

— Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit, or 8 x 8 bit

— Four separate interrupt channels for Rx, Tx, error, and wake-up

— Low-pass filter wake-up function

— Loop-back for self test operation

• Timer module (TIM):

— 8-channel timer

— Each channel configurable as either input capture or output compare

— Simple PWM mode

— Modulo reset of timer counter

— 16-bit pulse accumulator

— External event counting

— Gated time accumulation

• PWM module:

— Programmable period and duty cycle

— 8-bit 6-channel or 16-bit 3-channel

— Separate control for each pulse width and duty cycle

— Center-aligned or left-aligned outputs

— Programmable clock select logic with a wide range of frequencies

— Fast emergency shutdown input

• Serial interfaces:

— One asynchronous serial communications interface (SCI)

— One synchronous serial peripheral interface (SPI)

• CRG (clock reset generator module)

— Windowed COP watchdog

— Real time interrupt

— Clock monitor

— Pierce or low current Colpitts oscillator

— Phase-locked loop clock frequency multiplier

— Limp home mode in absence of external clock

— Low power 0.5MHz to 16MHz crystal oscillator reference clock

• Operating frequency:

— 32MHz equivalent to 16MHz bus speed for single chip

— 32MHz equivalent to 16MHz bus speed in expanded bus modes

— Option of 9S12C Family: 50MHz equivalent to 25MHz bus speed

— All 9S12GC Family members allow a 50MHz operating frequency.

• Internal 2.5V regulator:

— Supports an input voltage range from 2.97V to 5.5V

— Low power mode capability

— Includes low voltage reset (LVR) circuitry

— Includes low voltage interrupt (LVI) circuitry

• 48-pin LQFP, 52-pin LQFP, or 80-pin QFP package:

— Up to 58 I/O lines with 5V input and drive capability (80-pin package)

— Up to 2 dedicated 5V input only lines (IRQ, XIRQ)

— 5V 8 A/D converter inputs and 5V I/O

• Development support:

— Single-wire background debug™ mode (BDM)

— On-chip hardware breakpoints

— Enhanced DBG12 debug features

How read the label of the NXP chip？What is the naming rules of NXP microcontrollers?

NXP Electronics components unboxing，humidity card changed color chip can used？

56800E 56F8xxx Microcontroller IC 16-Bit 32MHz 64KB (32K x 16) FLASH 48-LQFP (7x7)

56F8036 Description

The 56F8036 is a member of the 56800E core-based family of Digital Signal Controllers (DSCs). It

combines, on a single chip, the processing power of a DSP and the functionality of a microcontroller with

a flexible set of peripherals to create an extremely cost-effective solution. Because of its low cost,

configuration flexibility, and compact program code, the 56F8036 is well-suited for many applications.

The 56F8036 includes many peripherals that are especially useful for industrial control, motion control,

home appliances, general purpose inverters, smart sensors, fire and security systems, switched-mode

power supply, power management, and medical monitoring applications.

The 56800E core is based on a dual Harvard-style architecture consisting of three execution units

operating in parallel, allowing as many as six operations per instruction cycle. The MCU-style

programming model and optimized instruction set allow straightforward generation of efficient, compact

DSP and control code. The instruction set is also highly efficient for C compilers to enable rapid

development of optimized control applications.

The 56F8036 supports program execution from internal memories. Two data operands can be accessed

from the on-chip data RAM per instruction cycle. The 56F8036 also offers up to 39 General Purpose

Input/Output (GPIO) lines, depending on peripheral configuration.

The 56F8036 Digital Signal Controller includes 64KB of Program Flash and 8KB of Unified

Data/Program RAM. Program Flash memory can be independently bulk erased or erased in pages.

Program Flash page erase size is 512 Bytes (256 Words).

A full set of programmable peripherals—PWM, ADCs, QSCI, QSPI, I2C, PITs, Quad Timers, DACs, and

analog comparators—supports various applications. Each peripheral can be independently shut down to

save power. Any pin in these peripherals can also be used as General Purpose Input/Outputs (GPIOs). 

56F8036 Features

1 Digital Signal Controller Core

• Efficient 16-bit 56800E family Digital Signal Controller (DSC) engine with dual Harvard architecture

• As many as 32 Million Instructions Per Second (MIPS) at 32MHz core frequency

• Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC)

• Four 36-bit accumulators, including extension bits

• 32-bit arithmetic and logic multi-bit shifter

• Parallel instruction set with unique DSP addressing modes

• Hardware DO and REP loops

• Three internal address buses

• Four internal data buses

• Instruction set supports both DSP and controller functions

• Controller-style addressing modes and instructions for compact code

• Efficient C compiler and local variable support

• Software subroutine and interrupt stack with depth limited only by memory

• JTAG/Enhanced On-Chip Emulation (OnCE) for unobtrusive, processor speed-independent, real-time

debugging

2 Memory

• Dual Harvard architecture permits as many as three simultaneous accesses to program and data memory

• Flash security and protection that prevent unauthorized users from gaining access to the internal Flash

• On-chip memory

— 64KB of Program Flash

— 8KB of Unified Data/Program RAM

• EEPROM emulation capability using Flash

3 Peripheral Circuits for 56F8036

• One multi-function six-output Pulse Width Modulator (PWM) module

— Up to 96MHz PWM operating clock

— 15 bits of resolution

— Center-aligned and edge-aligned PWM signal mode

— Four programmable fault inputs with programmable digital filter

— Double-buffered PWM registers

— Each complementary PWM signal pair allows selection of a PWM supply source from:

– PWM generator

– External GPIO

– Internal timers

– Analog comparator outputs

– ADC conversion result which compares with values of ADC high- and low-limit registers to set

PWM output

• Two independent 12-bit Analog-to-Digital Converters (ADCs)

— 2 x 5 channel inputs

— Supports both simultaneous and sequential conversions

— ADC conversions can be synchronized by both PWM and timer modules

— Sampling rate up to 2.67MSPS

— 16-word result buffer registers

• Two internal 12-bit Digital-to-Analog Converters (DACs)

— 2 microsecond settling time when output swing from rail to rail

— Automatic waveform generation generates square, triangle and sawtooth waveforms with

programmable period, update rate, and range

• One 16-bit multi-purpose Quad Timer module (TMR)

— Up to 96MHz operating clock

— Eight independent 16-bit counter/timers with cascading capability

— Each timer has capture and compare capability

— Up to 12 operating modes

• One Queued Serial Communication Interface (QSCI) with LIN Slave functionality

— Full-duplex or single-wire operation

— Two receiver wake-up methods:

– Idle line

– Address mark

— Four-bytes-deep FIFOs are available on both transmitter and receiver

• One Queued Serial Peripheral Interfaces (QSPI)

— Full-duplex operation

— Master and slave modes

— Four-words-deep FIFOs available on both transmitter and receiver

— Programmable Length Transactions (2 to 16 bits)

• One Inter-Integrated Circuit (I2C) port

— Operates up to 400kbps

— Supports both master and slave operation

— Supports both 10-bit address mode and broadcasting mode

• One Freescale scalable controller area network (MSCAN) module

— Fully compliant with CAN protocol - Version 2.0 A/B

— Supports standard and extended data frames

— Supports data rate up to 1Mbps

— Five receive buffers and three transmit buffers

• Three 16-bit Programmable Interval Timers (PITs)

• Two analog Comparators (CMPs)

— Selectable input source includes external pins, DACs

— Programmable output polarity

— Output can drive Timer input, PWM fault input, PWM source, external pin output and trigger ADCs

— Output falling and rising edge detection able to generate interrupts

• Computer Operating Properly (COP)/Watchdog timer capable of selecting different clock sources

• Up to 39 General-Purpose I/O (GPIO) pins with 5V tolerance

• Integrated Power-On Reset (POR) and Low-Voltage Interrupt (LVI) module

• Phase Lock Loop (PLL) provides a high-speed clock to the core and peripherals

• Clock sources:

— On-chip relaxation oscillator

— External clock: crystal oscillator, ceramic resonator and external clock source

• JTAG/EOnCE debug programming interface for real-time debugging

4 Energy Information

• Fabricated in high-density CMOS with 5V tolerance

• On-chip regulators for digital and analog circuitry to lower cost and reduce noise

• Wait and Stop modes available

• ADC smart power management

• Each peripheral can be individually disabled to save power

NXP Electronics components unboxing，humidity card changed color chip can used？

HCS12 HCS12 Microcontroller IC 16-Bit 25MHz 256KB (256K x 8) FLASH 112-LQFP (20x20)

MC9S12DT256

Covers also

MC9S12A256, MC9S12DJ256

MC9S12DG256,

Overview

The MC9S12DT256 microcontroller unit (MCU) is a 16-bit device composed of standard on-chip

peripherals including a 16-bit central processing unit (HCS12 CPU), 256K bytes of Flash EEPROM, 12K

bytes of RAM, 4K bytes of EEPROM, two asynchronous serial communications interfaces (SCI), three

serial peripheral interfaces (SPI), an 8-channel IC/OC enhanced capture timer, two 8-channel, 10-bit

analog-to-digital converters (ADC), an 8-channel pulse-width modulator (PWM), a digital Byte Data Link

Controller (BDLC), 29 discrete digital I/O channels (Port A, Port B, Port K and Port E), 20 discrete digital

I/O lines with interrupt and wakeup capability, three CAN 2.0 A, B software compatible modules

(MSCAN12), and an Inter-IC Bus. The MC9S12DT256 has full 16-bit data paths throughout. However,

the external bus can operate in an 8-bit narrow mode so single 8-bit wide memory can be interfaced for

lower cost systems. The inclusion of a PLL circuit allows power consumption and performance to be

adjusted to suit operational requirements.

Features

• HCS12 Core

– 16-bit HCS12 CPU

i. Upward compatible with M68HC11 instruction set

ii. Interrupt stacking and programmer’s model identical to M68HC11

iii.Instruction queue

iv. Enhanced indexed addressing

– MEBI (Multiplexed External Bus Interface)

– MMC (Module Mapping Control)

– INT (Interrupt control)

– BKP (Breakpoints)

– BDM (Background Debug Mode)

• CRG

– Low current Colpitts or Pierce oscillator

– PLL

– COP watchdog

– Real time interrupt

– Clock Monitor

• 8-bit and 4-bit ports with interrupt functionality

– Digital filtering

– Programmable rising or falling edge trigger

• Memory

– 256K Flash EEPROM

– 4K byte EEPROM

– 12K byte RAM

• Two 8-channel Analog-to-Digital Converters

– 10-bit resolution

– External conversion trigger capability

• Three 1M bit per second, CAN 2.0 A, B software compatible modules

– Five receive and three transmit buffers

– Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit or 8 x 8 bit

– Four separate interrupt channels for Rx, Tx, error and wake-up

– Low-pass filter wake-up function

– Loop-back for self test operation

• Enhanced Capture Timer

– 16-bit main counter with 7-bit prescaler

– 8 programmable input capture or output compare channels

– Four 8-bit or two 16-bit pulse accumulators

• 8 PWM channels

– Programmable period and duty cycle

– 8-bit 8-channel or 16-bit 4-channel

– Separate control for each pulse width and duty cycle

– Center-aligned or left-aligned outputs

– Programmable clock select logic with a wide range of frequencies

– Fast emergency shutdown input

– Usable as interrupt inputs

• Serial interfaces

– Two asynchronous Serial Communications Interfaces (SCI)

– Three Synchronous Serial Peripheral Interface (SPI)

• Byte Data Link Controller (BDLC)

– SAE J1850 Class B Data Communications Network Interface Compatible and ISO Compatible

for Low-Speed (<125 Kbps) Serial Data Communications in Automotive Applications

• Inter-IC Bus (IIC)

– Compatible with I2C Bus standard

– Multi-master operation

– Software programmable for one of 256 different serial clock frequencies

• 112-Pin LQFP package

– I/O lines with 5V input and drive capability

– 5V A/D converter inputs

– Operation at 50MHz equivalent to 25MHz Bus Speed

– Development support

– Single-wire background debug™ mode (BDM)

– On-chip hardware breakpoints

How read the label of the NXP chip？What is the naming rules of NXP microcontrollers?

S12Z S12 MagniV Microcontroller IC 16-Bit 32MHz 128KB (128K x 8) FLASH 48-LQFP (7x7)

Introduction

The MC9S12ZVL-Family is an automotive 16-bit microcontroller family using the180nm NVM+UHV

technology that offers the capability to integrate 40V analog components. This family reuses many

features from the existing S12 portfolio. The particular differentiating features of this family are the

enhanced S12Z core and the integration of “high-voltage”analog modules, including the voltage regulator

(VREG) and a Local Interconnect Network (LIN) physical layer.

The MC9S12ZVL-Family includes error correction code (ECC) on RAM, FLASH and EEPROM for

diagnostic or data storage, a fast analog-to-digital converter (ADC) and a frequency modulated phase

locked loop (IPLL) that improves the EMC performance. The MC9S12ZVL-Family delivers an optimized

solution with the integration of several key system components into a single device, optimizing system

architecture and achieving significant space savings. TheMC9S12ZVL-Family delivers all the advantages

and efficiencies of a 16-bit MCU while retaining the low cost, power consumption, EMC, and code-size

efficieney advantages currently enjoyed by users of existing S12 families. The MC9S12ZVL-Family is

available in 48-pin, 32-pin LQFP and 32-pin QFN-EP. In addition to the I/O ports available in each

module, further I/O ports are available with interrupt capability allowing wake-up from stop or wait

modes.

The MC9S12ZVL-Family is a general-purpose family of devices suitable for a wide range of applications.

The MC9S12ZVL-Family is targeted at generic automotive applications requiring LIN connectivity.

Typical examples of these applications include switch panels and body endpoints for sensors.

Chip-Level Features

On-chip modules available within the family include the following features:

·S12Z CPU core

·128, 96, 64, 32, 16 or 8 KB on-chip flash with ECC

·2048,1024,128 byte EEPROM with ECC

·8192,4096, 1024 or 512 byte on-chip SRAM with ECC

·Phase locked loop (IPLL) frequency multiplier with internal filter

·1 MHz internal RC oscillator with +/-1.3% accuracy over rated temperature range

·4-20MHz amplitude controlled pierce oscillator

·Internal COP (watchdog) module

·analog-to-digital converter (ADC) with 10-bit or 12-bit resolution and up to 10 channels available

on external pins and Vbg (bandgap) result reference

·PGA module with two input channels

·One 8-bit 5V digital-to-analog converter (DAC)

·One analog comparators (ACMP) with rail-to-rail inputs

·MSCAN(1Mbit/s, CAN2.0 A, B software compatible) module

·One serial peripheral interface (SPI) module

·One serial communication interface (SCI) module with interface to internal LIN physical layer

transceiver (with RX connected to a timer channel for frequency calibration purposes, if desired)

·Up to one additional SCI (not connected to LIN physical layer)

·One on-chip LIN physical layer transceiver fully compliant with the LIN 2.2 standard

·6-channel timer module (TIM0) with input capture/output compare

·2-channel timer module (TIM1) with input capture/output compare

·Inter-IC (IIC) module

·8-channel Pulse Width Modulation module (PWM)

·On-chip voltage regulator (VREG) for regulation of input supply and all internal voltages

·Autonomous periodic interrupt (API), supports cyclic wakeup from Stop mode

·Pins to support 25mA drive strength to VSSX

·Pin to support 20mA drive strength from VDDX (EVDD)

·High Voltage Input (HVI)

·Supply voltage sense with low battery warning

·On-chip temperature sensor, temperature value can be measured with ADC or can generate a high

temperature warning

· Up to 23 pins can be used as keyboard wake-up interrupt (KWI)

NXP Electronics components unboxing，humidity card changed color chip can used？