56800 56F8xx Microcontroller IC 16-Bit 80MHz 120KB (60K x 16) FLASH 160-MAPBGA (15x15)

56F807 Description

The 56F807 is a member of the 56800 core-based family of processors. It combines, on a single chip, the

processing power of a DSP and the functionality of a microcontroller with a flexible set of peripherals to

create an extremely cost-effective solution. Because of its low cost, configuration flexibility, and compact

program code, the 56F807 is well-suited for many applications. The 56F807 includes many peripherals

that are especially useful for applications such as motion control, smart appliances, steppers, encoders,

tachometers, limit switches, power supply and control, automotive control, engine management, noise

suppression, remote utility metering, industrial control for power, lighting, and automation.

The 56800 core is based on a Harvard-style architecture consisting of three execution units operating in

parallel, allowing as many as six operations per instruction cycle. The MCU-style programming model and

optimized instruction set allow straightforward generation of efficient, compact DSP and control code.

The instruction set is also highly efficient for C/C++ Compilers to enable rapid development of optimized

control applications.

The 56F807 supports program execution from either internal or external memories. Two data operands can

be accessed from the on-chip Data RAM per instruction cycle. The 56F807 also provides two external

dedicated interrupt lines and up to 32 General Purpose Input/Output (GPIO) lines, depending on peripheral

configuration.

The 56F807 controller includes 60K, 16-bit words of Program Flash and 8K words of Data Flash (each

programmable through the JTAG port) with 2K words of Program RAM and 4K words of Data RAM. It

also supports program execution from external memory. 

A total of 2K words of Boot Flash is incorporated for easy customer-inclusion of field-programmable

software routines that can be used to program the main Program and Data Flash memory areas. Both

Program and Data Flash memories can be independently bulk erased or erased in page sizes of 256 words.

The Boot Flash memory can also be either bulk or page erased.

A key application-specific feature of the 56F807 is the inclusion of two Pulse Width Modulator (PWM)

modules. These modules each incorporate three complementary, individually programmable PWM signal

outputs (each module is also capable of supporting six independent PWM functions, for a total of 12 PWM

outputs) to enhance motor control functionality. Complementary operation permits programmable dead

time insertion, distortion correction via current sensing by software, and separate top and bottom output

polarity control. The up-counter value is programmable to support a continuously variable PWM

frequency. Edge- and center-aligned synchronous pulse width control (0% to 100% modulation) is

supported. The device is capable of controlling most motor types: ACIM (AC Induction Motors), both

BDC and BLDC (Brush and Brushless DC motors), SRM and VRM (Switched and Variable Reluctance

Motors), and stepper motors. The PWMs incorporate fault protection and cycle-by-cycle current limiting

with sufficient output drive capability to directly drive standard optoisolators. A “smoke-inhibit”,

write-once protection feature for key parameters is also included. A patented PWM waveform distortion

correction circuit is also provided. Each PWM is double-buffered and includes interrupt controls to permit

integral reload rates to be programmable from 1 to 16. The PWM modules provide a reference output to

synchronize the analog-to-digital converters.

The 56F807 incorporates two separate Quadrature Decoders capable of capturing all four transitions on

the two-phase inputs, permitting generation of a number proportional to actual position. Speed

computation capabilities accommodate both fast- and slow-moving shafts. An integrated watchdog timer

in the Quadrature Decoder can be programmed with a time-out value to alarm when no shaft motion is

detected. Each input is filtered to ensure only true transitions are recorded.

This controller also provides a full set of standard programmable peripherals that include two Serial

Communications Interfaces (SCI), one Serial Peripheral Interface (SPI), and four Quad Timers. Any of

these interfaces can be used as General-Purpose Input/Outputs (GPIO) if that function is not required. A

Controller Area Network interface (CAN Version 2.0 A/B-compliant), an internal interrupt controller, and

14 dedicated GPIO lines are also included on the 56F807.

56F807 Features

1 Processing Core

• Efficient 16-bit 56800 family controller engine with dual Harvard architecture

• As many as 40 Million Instructions Per Second (MIPS) at 80MHz core frequency

• Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC)

• Two 36-bit accumulators including extension bits

• 16-bit bidirectional barrel shifter

• Parallel instruction set with unique processor addressing modes

• Hardware DO and REP loops

• Three internal address buses and one external address bus

• Four internal data buses and one external data bus

• Instruction set supports both DSP and controller functions

• Controller style addressing modes and instructions for compact code

• Efficient C compiler and local variable support

• Software subroutine and interrupt stack with depth limited only by memory

• JTAG/OnCE debug programming interface

2 Memory

• Harvard architecture permits as many as three simultaneous accesses to Program and Data memory

• On-chip memory including a low-cost, high-volume Flash solution

— 60K × 16-bit words of Program Flash

— 2K × 16-bit words of Program RAM

— 8K × 16-bit words of Data Flash

— 4K × 16-bit words of Data RAM

— 2K × 16-bit words of Boot Flash

• Off-chip memory expansion capabilities programmable for 0, 4, 8, or 12 wait states

— As much as 64K × 16 bits of Data memory

— As much as 64K × 16 bits of Program memory

3 Peripheral Circuits for 56F807

• Two Pulse Width Modulator modules each with six PWM outputs, three Current Sense inputs, and four

Fault inputs, fault tolerant design with dead time insertion, supports both center- and edge-aligned modes

• Four 12-bit, Analog-to-Digital Converters (ADCs), which support four simultaneous conversions with

quad, 4-pin multiplexed inputs; ADC and PWM modules can be synchronized

• Two Quadrature Decoders each with four inputs or two additional Quad Timers

• Two dedicated General Purpose Quad Timers totaling six pins: Timer C with two pins and Timer D with

four pins

• CAN 2.0 B Module with 2-pin port for transmit and receive

• Two Serial Communication Interfaces each with two pins (or four additional GPIO lines)

• Serial Peripheral Interface (SPI) with configurable 4-pin port (or four additional GPIO lines)

• Computer-Operating Properly (COP) Watchdog timer

• Two dedicated external interrupt pins

• 14 dedicated General Purpose I/O (GPIO) pins, 18 multiplexed GPIO pins

• External reset input pin for hardware reset

• External reset output pin for system reset

• JTAG/On-Chip Emulation (OnCE™) for unobtrusive, processor speed-independent debugging

• Software-programmable, Phase Locked Loop-based frequency synthesizer for the controller core clock

4 Energy Information

• Fabricated in high-density CMOS with 5V-tolerant, TTL-compatible digital inputs

• Uses a single 3.3V power supply

• On-chip regulators for digital and analog circuitry to lower cost and reduce noise

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• Wait and Stop modes available

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S12Z S12 MagniV Microcontroller IC 16-Bit 32MHz 192KB (192K x 8) FLASH 48-LQFP (7x7)

Introduction

The MC9S12ZVC-Family is a new member of the S12 MagniV product line integrating a battery level

(12V) voltage regulator, supply voltage monitoring, high voltage inputs and a CAN physical interface.It's

primarily targeting at CAN nodes like sensors, switch panels or small actuators. It offers various

low-power modes and wakeup management to address state of the art power consumption requirements.

Some members of theMC9S12ZVC-Family are also offered for high temperature applications requiring

AEC-Q100 Grade 0 (-40℃ to +150C ambient operating temperature range).

The MC9S12ZVC-Family is based on the enhanced performance, linear address space S12Z core and

delivers an optimized solution with the integration of several key system components into a single device,

optimizing system architecture and achieving significant space savings.

Chip-Level Features

On-chip modules available within the family include the following features:

·S12Z CPU core

·Up to 192 Kbyte on-chip flash with ECC

·Up to 2 Kbyte EEPROM with ECC

·Up to 12Kbyte on-chip SRAM with ECC

·Phase locked loop (IPLL) frequency multiplier with internal filter

·1 MHz internal RC oscillator with +/-1.3% accuracy over rated temperature range

·4-20MHz amplitude controlled pierce oscillator

·Internal COP (watchdog) module

·Analog-to-digital converter (ADC) with 12-bit resolution and up to 16 channels available on

external pins

·Two analog comparators (ACMP) with rail-to-rail inputs

·One 8-bit 5V digital-to-analog converter (DAC)

·Up to two serial peripheral interface(SPI) modules

· Up to two serial communication interface (SCI) modules

·SENT Transmitter Interface

·MSCAN(1 Mbit/s,CAN 2.0 A, B software compatible) module

·One on-chip CAN physical layer module

·8-channel timer module (TIM0) with input capture/output compare

·4-channel timer module (TIM1) with input capture/output compare (fast max 64MHz)

·Inter-IC (IIC) module

·4-channel 16-bit Pulse Width Modulation module (PWM0)

·4-channel 16-bit Pulse Width Modulation module (PWM1) (fast max 64MHz)

·On-chip voltage regulator (VREG) for regulation of input supply and all internal voltages

·Autonomous periodic interrupt (API), supports cyclic wakeup from Stop mode

·Four pins to support 25 mA drive strength to VSSX

·One pin to support 20 mA drive strength from VDDX (EVDD)

·Two High Voltage Input(HVI) pins

·Supply Vsup monitoring with warning

·On-chip temperature sensor, temperature value can be measured with ADC or can generate a high

temperature interrupt

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HCS12 HCS12 Microcontroller IC 16-Bit 25MHz 32KB (32K x 8) FLASH 80-QFP (14x14)

Introduction

The MC9S12C-Family / MC9S12GC-Family are 48/52/80 pin Flash-based MCU families, which deliver

the power and flexibility of the 16-bit core to a whole new range of cost and space sensitive, general

purpose industrial and automotive network applications. All MC9S12C-Family / MC9S12GC-Family

members feature standard on-chip peripherals including a 16-bit central processing unit (CPU12), up to

128K bytes of Flash EEPROM, up to 4K bytes of RAM, an asynchronous serial communications interface

(SCI), a serial peripheral interface (SPI), an 8-channel 16-bit timer module (TIM), a 6-channel 8-bit pulse

width modulator (PWM), an 8-channel, 10-bit analog-to-digital converter (ADC).

The MC9S12C128-Family members also feature a CAN 2.0 A, B software compatible module

(MSCAN12).

All MC9S12C-Family / MC9S12GC-Family devices feature full 16-bit data paths throughout. The

inclusion of a PLL circuit allows power consumption and performance to be adjusted to suit operational

requirements. In addition to the I/O ports available in each module, up to 10 dedicated I/O port bits are

available with wake-up capability from stop or wait mode. The devices are available in 48-, 52-, and 80-

pin QFP packages, with the 80-pin version pin compatible to the HCS12 A, B, and D Family derivatives.

Features

• 16-bit HCS12 core:

— HCS12 CPU

– Upward compatible with M68HC11 instruction set

– Interrupt stacking and programmer’s model identical to M68HC11

– Instruction queue

– Enhanced indexed addressing

— MMC (memory map and interface)

— INT (interrupt control)

— BDM (background debug mode)

— DBG12 (enhanced debug12 module, including breakpoints and change-of-flow trace buffer)

— MEBI (multiplexed expansion bus interface) available only in 80-pin package version

• Wake-up interrupt inputs:

— Up to 12 port bits available for wake up interrupt function with digital filtering

• Memory options:

— 16K or 32Kbyte Flash EEPROM (erasable in 512-byte sectors)

64K, 96K, or 128Kbyte Flash EEPROM (erasable in 1024-byte sectors)

— 1K, 2K or 4K Byte RAM

• Analog-to-digital converters:

— One 8-channel module with 10-bit resolution

— External conversion trigger capability

• Available on MC9S12C Family:

— One 1M bit per second, CAN 2.0 A, B software compatible module

— Five receive and three transmit buffers

— Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit, or 8 x 8 bit

— Four separate interrupt channels for Rx, Tx, error, and wake-up

— Low-pass filter wake-up function

— Loop-back for self test operation

• Timer module (TIM):

— 8-channel timer

— Each channel configurable as either input capture or output compare

— Simple PWM mode

— Modulo reset of timer counter

— 16-bit pulse accumulator

— External event counting

— Gated time accumulation

• PWM module:

— Programmable period and duty cycle

— 8-bit 6-channel or 16-bit 3-channel

— Separate control for each pulse width and duty cycle

— Center-aligned or left-aligned outputs

— Programmable clock select logic with a wide range of frequencies

— Fast emergency shutdown input

• Serial interfaces:

— One asynchronous serial communications interface (SCI)

— One synchronous serial peripheral interface (SPI)

• CRG (clock reset generator module)

— Windowed COP watchdog

— Real time interrupt

— Clock monitor

— Pierce or low current Colpitts oscillator

— Phase-locked loop clock frequency multiplier

— Limp home mode in absence of external clock

— Low power 0.5MHz to 16MHz crystal oscillator reference clock

• Operating frequency:

— 32MHz equivalent to 16MHz bus speed for single chip

— 32MHz equivalent to 16MHz bus speed in expanded bus modes

— Option of 9S12C Family: 50MHz equivalent to 25MHz bus speed

— All 9S12GC Family members allow a 50MHz operating frequency.

• Internal 2.5V regulator:

— Supports an input voltage range from 2.97V to 5.5V

— Low power mode capability

— Includes low voltage reset (LVR) circuitry

— Includes low voltage interrupt (LVI) circuitry

• 48-pin LQFP, 52-pin LQFP, or 80-pin QFP package:

— Up to 58 I/O lines with 5V input and drive capability (80-pin package)

— Up to 2 dedicated 5V input only lines (IRQ, XIRQ)

— 5V 8 A/D converter inputs and 5V I/O

• Development support:

— Single-wire background debug™ mode (BDM)

— On-chip hardware breakpoints

— Enhanced DBG12 debug features

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