NXP USA Inc.

S12Z S12 MagniV Microcontroller IC 16-Bit 32MHz 32KB (32K x 8) FLASH 32-HVQFN (5x5)

Introduction

The MC9S12ZVL-Family is an automotive 16-bit microcontroller family using the 180nm NVM +UHV

technology that offers the capability to integrate 40V analog components. This family reuses many

features from the existing S12 portfolio. The particular differentiating features of this family are the

enhanced S12Z core and the integration of“high-voltage”analog modules, including the voltage regulator

(VREG) and a Local Interconnect Network (LIN) physical layer.

The MC9S12ZVL-Family includes error correction code (ECC) on RAM, FLASH and EEPROM for

diagnostic or data storage, a fast analog-to-digital converter (ADC) and a frequency modulated phase

locked loop (IPLL) that improves the EMC performance. The MC9S12ZVL-Family delivers an optimized

solution with the integration of several key system components into a single device, optimizing system

architecture and achieving significant space savings. The MC9S12ZVL-Family delivers all the advantages

and efficiencies of a 16-bit MCU while retaining the low cost, power consumption, EMC, and code-size

efficiency advantages currently enjoyed by users of existing S12 families. The MC9S12ZVL-Family is

available in 48-pin, 32-pin LQFPand 32-pin QFN-EP. In addition to the I/O ports available in each

module, further I/O ports are available with interrupt capability allowing wake-up from stop or wait

modes.

The MC9S12ZVL-Family is a general-purpose family of devices suitable for a wide range ofapplications.

The MC9S12ZVL-Family is targeted at generic automotive applications requiring LIN connectivity.

Typical examples of these applications include switch panels and body endpoints for sensors.

Chip-Level Features

On-chip modules available within the family include the following features:

•S12Z CPU core 

•128, 96, 64, 32, 16 or 8 KB on-chip flash with ECC

•2048, 1024, 128 byte EEPROM with ECC

•8192, 4096, 1024 or 512 byte on-chip SRAM with ECC

•Phase locked loop (IPLL) frequency multiplier with internal filter

•1 MHz internal RC oscillator with +/-1.3% accuracy over rated temperature range

•4-20 MHz amplitude controlled pierce oscillator

•Internal COP (watchdog) module 

•analog-to-digital converter (ADC) with 10 -bit or 12 -bit resolution and up to 10 channels available 

 on external pins and Vbg (bandgap) result reference

•PGA module with two input channels

•One 8-bit 5V digital-to-analog converter (DAC)

•One analog comparators (ACMP) with rail-to-rail inputs

•MSCAN (1 Mbit/s, CAN 2.0 A, B software compatible) module

•One serial peripheral interface (SPI) module

•One serial communication interface (SCI) module with interface to internal LIN physical layer 

 transceiver (with RX connected to a timer channel for frequency calibration purposes, if desired)

•Up to one additional SCI (not connected to LIN physical layer)

•One on-chip LIN physical layer transceiver fully compliant with the LIN 2.2 standard

•6-channel timer module (TIM0) with input capture/output compare

•2-channel timer module (TIM1) with input capture/output compare

•Inter-IC (IIC) module

•8-channel Pulse Width Modulation module (PWM)

•On-chip voltage regulator (VREG) for regulation of input supply and all internal voltages

•Autonomous periodic interrupt (API), supports cyclic wakeup from Stop mode

•Pins to support 25 mA drive strength to VSSX

•Pin to support 20 mA drive strength from VDDX (EVDD)

•High Voltage Input (HVI)

•Supply voltage sense with low battery warning

•On-chip temperature sensor, temperature value can be measured with ADC or can generate a high 

 temperature warning

•Up to 23 pins can be used as keyboard wake-up interrupt (KWI)

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HCS12 HCS12 Microcontroller IC 16-Bit 25MHz 64KB (64K x 8) FLASH 112-LQFP (20x20)

MC9S12DJ64

Covers also

MC9S12D64, MC9S12A64, 

MC9S12D32,MC9S12A32

Overview

The MC9S12DJ64 microcontroller unit (MCU) is a 16-bit device composed of standard on-chip

peripherals including a 16-bit central processing unit (HCS12 CPU), 64K bytes of Flash EEPROM, 4K

bytes of RAM, 1K bytes of EEPROM, two asynchronous serial communications interfaces (SCI), one

serial peripheral interfaces (SPI), an 8-channel IC/OC enhanced capture timer, two 8-channel, 10-bit

analog-to-digital converters (ADC), an 8-channel pulse-width modulator (PWM), a digital Byte Data Link

Controller (BDLC), 29 discrete digital I/O channels (Port A, Port B, Port K and Port E), 20 discrete digital

I/O lines with interrupt and wakeup capability, a CAN 2.0 A, B software compatible modules

(MSCAN12), and an Inter-IC Bus. The MC9S12DJ64 has full 16-bit data paths throughout. However, the

external bus can operate in an 8-bit narrow mode so single 8-bit wide memory can be interfaced for lower

cost systems. The inclusion of a PLL circuit allows power consumption and performance to be adjusted to

suit operational requirements.

Features

• HCS12 Core

– 16-bit HCS12 CPU

i. Upward compatible with M68HC11 instruction set

ii. Interrupt stacking and programmer’s model identical to M68HC11

iii.Instruction queue

iv. Enhanced indexed addressing

– MEBI (Multiplexed External Bus Interface)

– MMC (Module Mapping Control)

– INT (Interrupt control)

– BKP (Breakpoints)

– BDM (Background Debug Mode)

• CRG (low current Colpitts or Pierce oscillator, PLL, reset, clocks, COP watchdog, real time

interrupt, clock monitor)

• 8-bit and 4-bit ports with interrupt functionality

– Digital filtering

– Programmable rising or falling edge trigger

• Memory

– 64K Flash EEPROM

– 1K byte EEPROM

– 4K byte RAM

• Two 8-channel Analog-to-Digital Converters

– 10-bit resolution

– External conversion trigger capability

• 1M bit per second, CAN 2.0 A, B software compatible module

– Five receive and three transmit buffers

– Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit or 8 x 8 bit

– Four separate interrupt channels for Rx, Tx, error and wake-up

– Low-pass filter wake-up function

– Loop-back for self test operation

• Enhanced Capture Timer

– 16-bit main counter with 7-bit prescaler

– 8 programmable input capture or output compare channels

– Four 8-bit or two 16-bit pulse accumulators

• 8 PWM channels

– Programmable period and duty cycle

– 8-bit 8-channel or 16-bit 4-channel

– Separate control for each pulse width and duty cycle

– Center-aligned or left-aligned outputs

– Programmable clock select logic with a wide range of frequencies

– Fast emergency shutdown input

– Usable as interrupt inputs

• Serial interfaces

– Two asynchronous Serial Communications Interfaces (SCI)

– Synchronous Serial Peripheral Interface (SPI)

• Byte Data Link Controller (BDLC)

– SAE J1850 Class B Data Communications Network Interface Compatible and ISO Compatible

for Low-Speed (<125 Kbps) Serial Data Communications in Automotive Applications

• Inter-IC Bus (IIC)

– Compatible with I2C Bus standard

– Multi-master operation

– Software programmable for one of 256 different serial clock frequencies

• 112-Pin LQFP or 80 QFP package

– I/O lines with 5V input and drive capability

– 5V A/D converter inputs

– Operation at 50MHz equivalent to 25MHz Bus Speed

– Development support

– Single-wire background debug™ mode (BDM)

– On-chip hardware breakpoints

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12V1 HCS12 Microcontroller IC 16-Bit 25MHz 96KB (96K x 8) FLASH 100-LQFP (14x14)

Introduction

The MC9S12G-Family is an optimized, automotive, 16-bit microcontroller product line focused on

low-cost, high-performance, and low pin-count. This family is intended to bridge between high-end 8-bit

microcontrollers and high-performance 16-bit microcontrollers, such as the MC9S12XS-Family. The

MC9S12G-Family is targeted at generic automotive applications requiring CAN or LIN/J2602

communication. Typical examples of these applications include body controllers, occupant detection, door

modules, seat controllers, RKE receivers, smart actuators, lighting modules, and smart junction boxes.

The MC9S12G-Family uses many of the same features found on the MC9S12XS- and MC9S12P-Family,

including error correction code (ECC) on flash memory, a fast analog-to-digital converter (ADC) and a

frequency modulated phase locked loop (IPLL) that improves the EMC performance. 

The MC9S12G-Family is optimized for lower program memory sizes down to 16k. In order to simplify

customer use it features an EEPROM with a small 4 bytes erase sector size.

The MC9S12G-Family deliver all the advantages and efficiencies of a 16-bit MCU while retaining the low

cost, power consumption, EMC, and code-size efficiency advantages currently enjoyed by users of NXP’s

existing 8-bit and 16-bit MCU families. Like the MC9S12XS-Family, the MC9S12G-Family run 16-bit

wide accesses without wait states for all peripherals and memories. The MC9S12G-Family is available in

100-pin LQFP, 64-pin LQFP, 48-pin LQFP/QFN, 32-pin LQFP and 20-pin TSSOP package options and

aims to maximize the amount of functionality especially for the lower pin count packages. In addition to

the I/O ports available in each module, further I/O ports are available with interrupt capability allowing

wake-up from stop or wait modes.

Chip-Level Features

On-chip modules available within the family include the following features:

• S12 CPU core

• Up to 240 Kbyte on-chip flash with ECC

• Up to 4 Kbyte EEPROM with ECC

• Up to 11 Kbyte on-chip SRAM

• Phase locked loop (IPLL) frequency multiplier with internal filter

• 4–16 MHz amplitude controlled Pierce oscillator

• 1 MHz internal RC oscillator

• Timer module (TIM) supporting up to eight channels that provide a range of 16-bit input capture,

output compare, counter, and pulse accumulator functions

• Pulse width modulation (PWM) module with up to eight x 8-bit channels

• Up to 16-channel, 10 or 12-bit resolution successive approximation analog-to-digital converter

(ADC)

• Up to two 8-bit digital-to-analog converters (DAC)

• Up to one 5V analog comparator (ACMP)

• Up to three serial peripheral interface (SPI) modules

• Up to three serial communication interface (SCI) modules supporting LIN communications

• Up to one multi-scalable controller area network (MSCAN) module (supporting CAN protocol

2.0A/B)

• On-chip voltage regulator (VREG) for regulation of input supply and all internal voltages

• Autonomous periodic interrupt (API)

• Precision fixed voltage reference for ADC conversions

• Optional reference voltage attenuator module to increase ADC accuracy