NXP USA Inc.

56800 56F8xx Microcontroller IC 16-Bit 80MHz 120KB (60K x 16) FLASH 160-LQFP (24x24)

56F807 Description

The 56F807 is a member of the 56800 core-based family of processors. It combines, on a single chip, the

processing power of a DSP and the functionality of a microcontroller with a flexible set of peripherals to

create an extremely cost-effective solution. Because of its low cost, configuration flexibility, and compact

program code, the 56F807 is well-suited for many applications. The 56F807 includes many peripherals

that are especially useful for applications such as motion control, smart appliances, steppers, encoders,

tachometers, limit switches, power supply and control, automotive control, engine management, noise

suppression, remote utility metering, industrial control for power, lighting, and automation.

The 56800 core is based on a Harvard-style architecture consisting of three execution units operating in

parallel, allowing as many as six operations per instruction cycle. The MCU-style programming model and

optimized instruction set allow straightforward generation of efficient, compact DSP and control code.

The instruction set is also highly efficient for C/C++ Compilers to enable rapid development of optimized

control applications.

The 56F807 supports program execution from either internal or external memories. Two data operands can

be accessed from the on-chip Data RAM per instruction cycle. The 56F807 also provides two external

dedicated interrupt lines and up to 32 General Purpose Input/Output (GPIO) lines, depending on peripheral

configuration.

The 56F807 controller includes 60K, 16-bit words of Program Flash and 8K words of Data Flash (each

programmable through the JTAG port) with 2K words of Program RAM and 4K words of Data RAM. It

also supports program execution from external memory. 

A total of 2K words of Boot Flash is incorporated for easy customer-inclusion of field-programmable

software routines that can be used to program the main Program and Data Flash memory areas. Both

Program and Data Flash memories can be independently bulk erased or erased in page sizes of 256 words.

The Boot Flash memory can also be either bulk or page erased.

A key application-specific feature of the 56F807 is the inclusion of two Pulse Width Modulator (PWM)

modules. These modules each incorporate three complementary, individually programmable PWM signal

outputs (each module is also capable of supporting six independent PWM functions, for a total of 12 PWM

outputs) to enhance motor control functionality. Complementary operation permits programmable dead

time insertion, distortion correction via current sensing by software, and separate top and bottom output

polarity control. The up-counter value is programmable to support a continuously variable PWM

frequency. Edge- and center-aligned synchronous pulse width control (0% to 100% modulation) is

supported. The device is capable of controlling most motor types: ACIM (AC Induction Motors), both

BDC and BLDC (Brush and Brushless DC motors), SRM and VRM (Switched and Variable Reluctance

Motors), and stepper motors. The PWMs incorporate fault protection and cycle-by-cycle current limiting

with sufficient output drive capability to directly drive standard optoisolators. A “smoke-inhibit”,

write-once protection feature for key parameters is also included. A patented PWM waveform distortion

correction circuit is also provided. Each PWM is double-buffered and includes interrupt controls to permit

integral reload rates to be programmable from 1 to 16. The PWM modules provide a reference output to

synchronize the analog-to-digital converters.

The 56F807 incorporates two separate Quadrature Decoders capable of capturing all four transitions on

the two-phase inputs, permitting generation of a number proportional to actual position. Speed

computation capabilities accommodate both fast- and slow-moving shafts. An integrated watchdog timer

in the Quadrature Decoder can be programmed with a time-out value to alarm when no shaft motion is

detected. Each input is filtered to ensure only true transitions are recorded.

This controller also provides a full set of standard programmable peripherals that include two Serial

Communications Interfaces (SCI), one Serial Peripheral Interface (SPI), and four Quad Timers. Any of

these interfaces can be used as General-Purpose Input/Outputs (GPIO) if that function is not required. A

Controller Area Network interface (CAN Version 2.0 A/B-compliant), an internal interrupt controller, and

14 dedicated GPIO lines are also included on the 56F807.

56F807 Features

1 Processing Core

• Efficient 16-bit 56800 family controller engine with dual Harvard architecture

• As many as 40 Million Instructions Per Second (MIPS) at 80MHz core frequency

• Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC)

• Two 36-bit accumulators including extension bits

• 16-bit bidirectional barrel shifter

• Parallel instruction set with unique processor addressing modes

• Hardware DO and REP loops

• Three internal address buses and one external address bus

• Four internal data buses and one external data bus

• Instruction set supports both DSP and controller functions

• Controller style addressing modes and instructions for compact code

• Efficient C compiler and local variable support

• Software subroutine and interrupt stack with depth limited only by memory

• JTAG/OnCE debug programming interface

2 Memory

• Harvard architecture permits as many as three simultaneous accesses to Program and Data memory

• On-chip memory including a low-cost, high-volume Flash solution

— 60K × 16-bit words of Program Flash

— 2K × 16-bit words of Program RAM

— 8K × 16-bit words of Data Flash

— 4K × 16-bit words of Data RAM

— 2K × 16-bit words of Boot Flash

• Off-chip memory expansion capabilities programmable for 0, 4, 8, or 12 wait states

— As much as 64K × 16 bits of Data memory

— As much as 64K × 16 bits of Program memory

3 Peripheral Circuits for 56F807

• Two Pulse Width Modulator modules each with six PWM outputs, three Current Sense inputs, and four

Fault inputs, fault tolerant design with dead time insertion, supports both center- and edge-aligned modes

• Four 12-bit, Analog-to-Digital Converters (ADCs), which support four simultaneous conversions with

quad, 4-pin multiplexed inputs; ADC and PWM modules can be synchronized

• Two Quadrature Decoders each with four inputs or two additional Quad Timers

• Two dedicated General Purpose Quad Timers totaling six pins: Timer C with two pins and Timer D with

four pins

• CAN 2.0 B Module with 2-pin port for transmit and receive

• Two Serial Communication Interfaces each with two pins (or four additional GPIO lines)

• Serial Peripheral Interface (SPI) with configurable 4-pin port (or four additional GPIO lines)

• Computer-Operating Properly (COP) Watchdog timer

• Two dedicated external interrupt pins

• 14 dedicated General Purpose I/O (GPIO) pins, 18 multiplexed GPIO pins

• External reset input pin for hardware reset

• External reset output pin for system reset

• JTAG/On-Chip Emulation (OnCE™) for unobtrusive, processor speed-independent debugging

• Software-programmable, Phase Locked Loop-based frequency synthesizer for the controller core clock

4 Energy Information

• Fabricated in high-density CMOS with 5V-tolerant, TTL-compatible digital inputs

• Uses a single 3.3V power supply

• On-chip regulators for digital and analog circuitry to lower cost and reduce noise

• Wait and Stop modes available

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HCS12X HCS12X Microcontroller IC 16-Bit 80MHz 256KB (256K x 8) FLASH 112-LQFP (20x20)

MC9S12XDP512

Covers

S12XD, S12XB & S12XA Families

Introduction

The MC9S12XD family will retain the low cost, power consumption, EMC and code-size efficiency

advantages currently enjoyed by users of Freescale's existing 16-Bit MC9S12 MCU Family.

Based around an enhanced S12 core, the MC9S12XD family will deliver 2 to 5 times the performance of

a 25-MHz S12 whilst retaining a high degree of pin and code compatibility with the S12.

The MC9S12XD family introduces the performance boosting XGATE module. Using enhanced DMA

functionality, this parallel processing module offloads the CPU by providing high-speed data processing

and transfer between peripheral modules, RAM, Flash EEPROM and I/O ports. Providing up to 80 MIPS

of performance additional to the CPU, the XGATE can access all peripherals, Flash EEPROM and the

RAM block.

The MC9S12XD family is composed of standard on-chip peripherals including up to 512 Kbytes of Flash

EEPROM, 32 Kbytes of RAM, 4 Kbytes of EEPROM, six asynchronous serial communications interfaces

(SCI), three serial peripheral interfaces (SPI), an 8-channel IC/OC enhanced capture timer, an 8-channel,

10-bit analog-to-digital converter, a 16-channel, 10-bit analog-to-digital converter, an 8-channel

pulse-width modulator (PWM), five CAN 2.0 A, B software compatible modules (MSCAN12), two

inter-IC bus blocks, and a periodic interrupt timer. The MC9S12XD family has full 16-bit data paths

throughout.

The non-multiplexed expanded bus interface available on the 144-pin versions allows an easy interface to

external memories

The inclusion of a PLL circuit allows power consumption and performance to be adjusted to suit

operational requirements. System power consumption can be further improved with the new “fast exit from

stop mode” feature.

In addition to the I/O ports available in each module, up to 25 further I/O ports are available with interrupt

capability allowing wake-up from stop or wait mode.

Family members in 144-pin LQFP will be available with external bus interface and parts in 112-pin LQFP

or 80-pin QFP package without external bus interface. See Appendix E Derivative Differencesfor package

options.

MC9S12XD/B/A Family Features

• HCS12X Core

— 16-bit HCS12X CPU

– Upward compatible with MC9S12 instruction set

– Interrupt stacking and programmer’s model identical to MC9S12

– Instruction queue

– Enhanced indexed addressing

– Enhanced instruction set

— EBI (external bus interface)

— MMC (module mapping control)

— INT (interrupt controller)

— DBG (debug module to monitor HCS12X CPU and XGATE bus activity)

— BDM (background debug mode)

• XGATE (peripheral coprocessor)

— Parallel processing module off loads the CPU by providing high-speed data processing and

transfer

— Data transfer between Flash EEPROM, RAM, peripheral modules, and I/O ports

• PIT (periodic interrupt timer)

— Four timers with independent time-out periods

— Time-out periods selectable between 1 and 224 bus clock cycles

• CRG (clock and reset generator)

— Low noise/low power Pierce oscillator

— PLL

— COP watchdog

— Real time interrupt

— Clock monitor

— Fast wake-up from stop mode

• Port H & Port J with interrupt functionality

— Digital filtering

— Programmable rising or falling edge trigger

• Memory

— 512, 256 and 128-Kbyte Flash EEPROM

— 4 and 2-Kbyte EEPROM

— 32, 16 and 12-Kbyte RAM

• One 16-channel and one 8-channel ADC (analog-to-digital converter)

— 10-bit resolution

— External and internal conversion trigger capabilityFiveFourTwo 1M bit per second,

CAN 2.0 A, B software compatible modules

— Five receive and three transmit buffers

— Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit, or 8 x 8 bit

— Four separate interrupt channels for Rx, Tx, error, and wake-up

— Low-pass filter wake-up function

— Loop-back for self-test operation

• ECT (enhanced capture timer)

— 16-bit main counter with 7-bit prescaler

— 8 programmable input capture or output compare channels

— Four 8-bit or two 16-bit pulse accumulators

• 8 PWM (pulse-width modulator) channels

— Programmable period and duty cycle

— 8-bit 8-channel or 16-bit 4-channel

— Separate control for each pulse width and duty cycle

— Center-aligned or left-aligned outputs

— Programmable clock select logic with a wide range of frequencies

— Fast emergency shutdown input

• Serial interfaces

— SixFourTwo asynchronous serial communication interfaces (SCI) with additional LIN support

and selectable IrDA 1.4 return-to-zero-inverted (RZI) format with programmable pulse width

— ThreeTwo Synchronous Serial Peripheral Interfaces (SPI)

• TwoOne IIC (Inter-IC bus) Modules

— Compatible with IIC bus standard

— Multi-master operation

— Software programmable for one of 256 different serial clock frequencies

• On-Chip Voltage Regulator

— Two parallel, linear voltage regulators with bandgap reference

— Low-voltage detect (LVD) with low-voltage interrupt (LVI)

— Power-on reset (POR) circuit

— 3.3-V–5.5-V operation

— Low-voltage reset (LVR)

— Ultra low-power wake-up timer

• 144-pin LQFP, 112-pin LQFP, and 80-pin QFP packages

— I/O lines with 5-V input and drive capability

— Input threshold on external bus interface inputs switchable for 3.3-V or 5-V operation

— 5-V A/D converter inputs

— Operation at 80 MHz equivalent to 40-MHz bus speed

• Development support

— Single-wire background debug™ mode (BDM)

— Four on-chip hardware breakpoints

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