56800 56F8xx Microcontroller IC 16-Bit 60MHz 16KB (8K x 16) FLASH 48-LQFP (7x7)

56F801 Description

The 56F801 is a member of the 56800 core-based family of processors. It combines, on a single chip, the

processing power of a DSP and the functionality of a microcontroller with a flexible set of peripherals to

create an extremely cost-effective solution. Because of its low cost, configuration flexibility, and

compact program code, the 56F801 is well-suited for many applications. The 56F801 includes many

peripherals that are especially useful for applications such as motion control, smart appliances, steppers,

encoders, tachometers, limit switches, power supply and control, automotive control, engine

management, noise suppression, remote utility metering, and industrial control for power, lighting, and

automation.

The 56800 core is based on a Harvard-style architecture consisting of three execution units operating in

parallel, allowing as many as six operations per instruction cycle. The microprocessor-style programming

model and optimized instruction set allow straightforward generation of efficient, compact code for both

DSP and MCU applications. The instruction set is also highly efficient for C compilers to enable rapid

development of optimized control applications.

The 56F801 supports program execution from either internal or external memories. Two data operands can

be accessed from the on-chip Data RAM per instruction cycle. The 56F801 also provides one external

dedicated interrupt lines and up to 11 General Purpose Input/Output (GPIO) lines, depending on peripheral

configuration.

The 56F801 controller includes 8K words (16-bit) of Program Flash and 2K words of Data Flash (each

programmable through the JTAG port) with 1K words of both Program and Data RAM. A total of 2K

words of Boot Flash is incorporated for easy customer-inclusion of field-programmable software routines

that can be used to program the main Program and Data Flash memory areas. Both Program and Data Flash

memories can be independently bulk erased or erased in page sizes of 256 words. The Boot Flash memory

can also be either bulk or page erased.

A key application-specific feature of the 56F801 is the inclusion of a Pulse Width Modulator (PWM)

module. This modules incorporates six complementary, individually programmable PWM signal outputs

to enhance motor control functionality. Complementary operation permits programmable dead-time

insertion, and separate top and bottom output polarity control. The up-counter value is programmable to

support a continuously variable PWM frequency. Both edge- and center-aligned synchronous pulse width

control (0% to 100% modulation) are supported. The device is capable of controlling most motor types:

ACIM (AC Induction Motors), both BDC and BLDC (Brush and Brushless DC motors), SRM and VRM

(Switched and Variable Reluctance Motors), and stepper motors. The PWMs incorporate fault protection

and cycle-by-cycle current limiting with sufficient output drive capability to directly drive standard

opto-isolators. A “smoke-inhibit”, write-once protection feature for key parameters is also included. The

PWM is double-buffered and includes interrupt control to permit integral reload rates to be programmable

from 1 to 16. The PWM modules provide a reference output to synchronize the Analog-to-Digital

Converters.

The 56F801 incorporates an 8 input, 12-bit Analog-to-Digital Converter (ADC). A full set of standard

programmable peripherals is provided that include a Serial Communications Interface (SCI), a Serial

Peripheral Interface (SPI), and two Quad Timers. Any of these interfaces can be used as General-Purpose

Input/Outputs (GPIO) if that function is not required. An on-chip relaxation oscillator provides flexibility

in the choice of either on-chip or externally supplied frequency reference for chip timing operations.

Application code is used to select which source is to be used.

56F801 Features

Digital Signal Processing Core

• Efficient 16-bit 56800 family controller engine with dual Harvard architecture

• As many as 40 Million Instructions Per Second (MIPS) at 80MHz core frequency

• Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC)

• Two 36-bit accumulators including extension bits

• 16-bit bidirectional barrel shifter

• Parallel instruction set with unique processor addressing modes

• Hardware DO and REP loops

• Three internal address buses and one external address bus

• Four internal data buses and one external data bus

• Instruction set supports both DSP and controller functions

• Controller style addressing modes and instructions for compact code

• Efficient C compiler and local variable support

• Software subroutine and interrupt stack with depth limited only by memory

• JTAG/OnCE debug programming interface

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S12Z S12 MagniV Microcontroller IC 16-Bit 32MHz 32KB (32K x 8) FLASH 32-LQFP (7x7)

Introduction

The MC9S12ZVL-Family is an automotive 16-bit microcontroller family using the180nm NVM+UHV

technology that offers the capability to integrate 40V analog components. This family reuses many

features from the existing S12 portfolio. The particular differentiating features of this family are the

enhanced S12Z core and the integration of “high-voltage”analog modules, including the voltage regulator

(VREG) and a Local Interconnect Network (LIN) physical layer.

The MC9S12ZVL-Family includes error correction code (ECC) on RAM, FLASH and EEPROM for

diagnostic or data storage, a fast analog-to-digital converter (ADC) and a frequency modulated phase

locked loop (IPLL) that improves the EMC performance. The MC9S12ZVL-Family delivers an optimized

solution with the integration of several key system components into a single device, optimizing system

architecture and achieving significant space savings. The MC9S12ZVL-Family delivers all the advantages

and efficiencies of a 16-bit MCU while retaining the low cost, power consumption, EMC, and code-size

efficiency advantages currently enjoyed by users of existing S12 families. The MC9S12ZVL-Family is

available in 48-pin, 32-pin LQFPand 32-pin QFN-EP. In addition to the I/O ports available in each

module, further I/O ports are available with interrupt capability allowing wake-up from stop or wait

modes.

The MC9S12ZVL-Family is a general-purpose family ofdevices suitable for a wide range of applications.

The MC9S12ZVL-Family is targeted at generic automotive applications requiring LIN connectivity.

Typical examples of these applications include switch panels and body endpoints for sensors.

Chip-Level Features

On-chip modules available within the family include the following features:

S12Z CPU core

128, 96, 64, 32, 16 or 8 KB on-chip flash with ECC

2048,1024, 128 byte EEPROM with ECC

8192,4096, 1024 or 512 byte on-chip SRAM with ECC

Phase locked loop (IPLL) frequency multiplier with internal filter

1 MHz internal RC oscillator with +/-1.3% accuracy over rated temperature range

4-20MHz amplitude controlled pierce oscillator

Internal COP (watchdog) module

analog-to-digital converter (ADC) with 10-bit or 12-bit resolution and up to 10 channels available

on external pins and Vbg(bandgap) result reference

PGA module with two input channels

One 8-bit 5V digital-to-analog converter (DAC)

One analog comparators (ACMP) with rail-to-rail inputs

MSCAN(1Mbit/s, CAN2.0 A, B software compatible) module

One serial peripheral interface (SPI) module

One serial communication interface(SCI) module with interface to internal LIN physical layer

transceiver (with RX connected to a timer channel for frequency calibration purposes, if desired)

Up to one additional SCI (not connected to LIN physical layer)

One on-chip LIN physical layer transceiver fully compliant with the LIN 2.2 standard

6-channel timer module (TIM0) with input capture/output compare

2-channel timer module (TIM1) with input capture/output compare

Inter-IC (IIC) module

8-channel Pulse Width Modulation module (PWM)

On-chip voltage regulator (VREG) for regulation of input supply and all internal voltages

Autonomous periodic interrupt (API), supports cyclic wakeup from Stop mode

Pins to support 25 mA drive strength to VSSX

Pin to support 20 mA drive strength from VDDX (EVDD)

High Voltage Input (HVI)

Supply voltage sense with low battery warning

On-chip temperature sensor, temperature value can be measured with ADC or can generate a high

temperature warning

Up to 23 pins can be used as keyboard wake-up interrupt (KWI)

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S12 HCS12 Microcontroller IC 16-bit 25MHz 16KB(16K x 8) Flash 32-LQFP(7x7)

Introduction

The MC9S12G-Family is an optimized, automotive, 16-bit microcontroller product line focused on

low-cost, high-performance, and low pin-count. This family is intended to bridge between high-end 8-bit

microcontrollers and high-performance 16-bit microcontrollers, such as the MC9S12XS-Family. The

MC9S12G-Family is targeted at generic automotive applications requiring CAN or LIN/J2602

communication. Typical examples of these applications include body controllers, occupant detection, door

modules, seat controllers, RKE receivers, smart actuators, lighting modules, and smart junction boxes.

The MC9S12G-Family uses many of the same features found on the MC9S12XS- and MC9S12P-Family,

including error correction code (ECC) on flash memory, a fast analog-to-digital converter (ADC) and a

frequency modulated phase locked loop (IPLL) that improves the EMC performance. 

The MC9S12G-Family is optimized for lower program memory sizes down to 16k. In order to simplify

customer use it features an EEPROM with a small 4 bytes erase sector size.

The MC9S12G-Family deliver all the advantages and efficiencies of a 16-bit MCU while retaining the low

cost, power consumption, EMC, and code-size efficiency advantages currently enjoyed by users of NXP’s

existing 8-bit and 16-bit MCU families. Like the MC9S12XS-Family, the MC9S12G-Family run 16-bit

wide accesses without wait states for all peripherals and memories. The MC9S12G-Family is available in

100-pin LQFP, 64-pin LQFP, 48-pin LQFP/QFN, 32-pin LQFP and 20-pin TSSOP package options and

aims to maximize the amount of functionality especially for the lower pin count packages. In addition to

the I/O ports available in each module, further I/O ports are available with interrupt capability allowing

wake-up from stop or wait modes.

Chip-Level Features

On-chip modules available within the family include the following features:

• S12 CPU core

• Up to 240 Kbyte on-chip flash with ECC

• Up to 4 Kbyte EEPROM with ECC

• Up to 11 Kbyte on-chip SRAM

• Phase locked loop (IPLL) frequency multiplier with internal filter

• 4–16 MHz amplitude controlled Pierce oscillator

• 1 MHz internal RC oscillator

• Timer module (TIM) supporting up to eight channels that provide a range of 16-bit input capture,

output compare, counter, and pulse accumulator functions

• Pulse width modulation (PWM) module with up to eight x 8-bit channels

• Up to 16-channel, 10 or 12-bit resolution successive approximation analog-to-digital converter

(ADC)

• Up to two 8-bit digital-to-analog converters (DAC)

• Up to one 5V analog comparator (ACMP)

• Up to three serial peripheral interface (SPI) modules

• Up to three serial communication interface (SCI) modules supporting LIN communications

• Up to one multi-scalable controller area network (MSCAN) module (supporting CAN protocol

2.0A/B)

• On-chip voltage regulator (VREG) for regulation of input supply and all internal voltages

• Autonomous periodic interrupt (API)

• Precision fixed voltage reference for ADC conversions

• Optional reference voltage attenuator module to increase ADC accuracy

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HCS12 HCS12 Microcontroller IC 16-Bit 32MHz 32KB (32K x 8) FLASH 48-QFN-EP (7x7)

MC9S12P128

Covers also MC9S12P-Family

MC9S12P96

MC9S12P64

MC9S12P32

Introduction

The MC9S12P family is an optimized, automotive, 16-bit microcontroller product line focused on lowcost,

high-performance, and low pin-count. This family is intended to bridge between high-end 8-bit

microcontrollers and high-performance 16-bit microcontrollers, such as the MC9S12XS family. The

MC9S12P family is targeted at generic automotive applications requiring CAN or LIN/J2602

communication. Typical examples of these applications include body controllers, occupant detection, door

modules, seat controllers, RKE receivers, smart actuators, lighting modules, and smart junction boxes.

The MC9S12P family uses many of the same features found on the MC9S12XS family, including error

correction code (ECC) on flash memory, a separate data-flash module for diagnostic or data storage, a fast

analog-to-digital converter (ATD) and a frequency modulated phase locked loop (IPLL) that improves the

EMC performance.

The MC9S12P family deliver all the advantages and efficiencies of a 16-bit MCU while retaining the low

cost, power consumption, EMC, and code-size efficiency advantages currently enjoyed by users of

Freescale’s existing 8-bit and 16-bit MCU families. Like the MC9S12XS family, the MC9S12P family run

16-bit wide accesses without wait states for all peripherals and memories. The MC9S12P family is

available in 80-pin QFP, 64-pin LQFP, and 48-pin QFN package options and aims to maximize pin

compatibility with the MC9S12XS family. In addition to the I/O ports available in each module, further

I/O ports are available with interrupt capability allowing wake-up from stop or wait modes.

On-Chip Flash with ECC

On-chip flash memory on the MC9S12P features the following:

• Up to 128 Kbyte of program flash memory

— 32 data bits plus 7 syndrome ECC (error correction code) bits allow single bit error correction

and double fault detection

— Erase sector size 512 bytes

— Automated program and erase algorithm

— User margin level setting for reads

— Protection scheme to prevent accidental program or erase

• 4 Kbyte data flash space

— 16 data bits plus 6 syndrome ECC (error correction code) bits allow single bit error correction

and double fault detection

— Erase sector size 256 bytes

— Automated program and erase algorithm

— User margin level setting for reads

NXP Electronics components unboxing，humidity card changed color chip can used？