HCS12 HCS12 Microcontroller IC 16-Bit 25MHz 128KB (128K x 8) FLASH 112-LQFP (20x20)

Overview

The MC9S12DT128 microcontroller unit (MCU) is a 16-bit device composed of standard on-chip

peripherals including a 16-bit central processing unit (HCS12 CPU), 128K bytes of Flash EEPROM, 8K

bytes of RAM, 2K bytes of EEPROM, two asynchronous serial communications interfaces (SCI), two

serial peripheral interfaces (SPI), an 8-channel IC/OC enhanced capture timer, two 8-channel, 10-bit

analog-to-digital converters (ADC), an 8-channel pulse-width modulator (PWM), a digital Byte Data Link

Controller (BDLC), 29 discrete digital I/O channels (Port A, Port B, Port K and Port E), 20 discrete digital

I/O lines with interrupt and wakeup capability, three CAN 2.0 A, B software compatible modules

(MSCAN12), a Byteflight module and an Inter-IC Bus. The MC9S12DT128 has full 16-bit data paths

throughout. However, the external bus can operate in an 8-bit narrow mode so single 8-bit wide memory

can be interfaced for lower cost systems. The inclusion of a PLL circuit allows power consumption and

performance to be adjusted to suit operational requirements.

Features

• HCS12 Core

– 16-bit HCS12 CPU

i. Upward compatible with M68HC11 instruction set

ii. Interrupt stacking and programmer’s model identical to M68HC11

iii.20-bit ALU

iv. Instruction queue

v. Enhanced indexed addressing

– MEBI (Multiplexed External Bus Interface)

– MMC (Module Mapping Control)

– INT (Interrupt control)

– BKP (Breakpoints)

– BDM (Background Debug Module)

• CRG (Clock and Reset Generator)

– Choice of low current Colpitts oscillator or standard Pierce Oscillator

– PLL

– COP watchdog

– real time interrupt

– clock monitor

• 8-bit and 4-bit ports with interrupt functionality

– Digital filtering

– Programmable rising or falling edge trigger

• Memory

– 128K Flash EEPROM

– 2K byte EEPROM

– 8K byte RAM

• Two 8-channel Analog-to-Digital Converters

– 10-bit resolution

– External conversion trigger capability

• Three 1M bit per second, CAN 2.0 A, B software compatible modules

– Five receive and three transmit buffers

– Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit or 8 x 8 bit

– Four separate interrupt channels for Rx, Tx, error and wake-up

– Low-pass filter wake-up function

– Loop-back for self test operation

• Enhanced Capture Timer

– 16-bit main counter with 7-bit prescaler

– 8 programmable input capture or output compare channels

– Four 8-bit or two 16-bit pulse accumulators

• 8 PWM channels

– Programmable period and duty cycle

– 8-bit 8-channel or 16-bit 4-channel

– Separate control for each pulse width and duty cycle

– Center-aligned or left-aligned outputs

– Programmable clock select logic with a wide range of frequencies

– Fast emergency shutdown input

– Usable as interrupt inputs

• Serial interfaces

– Two asynchronous Serial Communications Interfaces (SCI)

– Two Synchronous Serial Peripheral Interface (SPI)

– Byteflight

• Byte Data Link Controller (BDLC)

• SAE J1850 Class B Data Communications Network Interface

– Compatible and ISO Compatible for Low-Speed (<125 Kbps) Serial Data Communications in

Automotive Applications

• Inter-IC Bus (IIC)

– Compatible with I2C Bus standard

– Multi-master operation

– Software programmable for one of 256 different serial clock frequencies

• 112-Pin LQFP and 80-Pin QFP package options

– I/O lines with 5V input and drive capability

– 5V A/D converter inputs

– Operation at 50MHz equivalent to 25MHz Bus Speed

– Development support

– Single-wire background debug™ mode

– On-chip hardware breakpoints

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56800E 56F8xxx Microcontroller IC 16-Bit 60MHz 32KB (16K x 16) FLASH 48-LQFP (7x7)

Device Description

The 56F8322 and 56F8122 are members of the 56800E core-based family of controllers. Each combines,

on a single chip, the processing power of a Digital Signal Processor (DSP) and the functionality of a

microcontroller with a flexible set of peripherals to create an extremely cost-effective solution. Because

of their low cost, configuration flexibility, and compact program code, the 56F8322 and 56F8122 are

well-suited for many applications. These devices include many peripherals that are especially useful for

automotive control (56F8322 only); industrial control and networking; motion control; home appliances;

general purpose inverters; smart sensors; fire and security systems; power management; and medical

monitoring applications.

The 56800E core is based on a Harvard-style architecture consisting of three execution units operating in

parallel, allowing as many as six operations per instruction cycle. The MCU-style programming model and

optimized instruction set allow straightforward generation of efficient, compact DSP and control code.

The instruction set is also highly efficient for C Compilers to enable rapid development of optimized

control applications.

The 56F8322 and 56F8122 support program execution from internal memories. Two data operands can be

accessed from the on-chip data RAM per instruction cycle. These devices also provide one external

dedicated interrupt line and up to 21 General Purpose Input/Output (GPIO) lines, depending on peripheral

configuration.

56F8322 Features

The 56F8322 controller includes 32KB of Program Flash and 8KB of Data Flash, each programmable

through the JTAG port, and 4KB of Program RAM and 8KB of Data RAM. A total of 8KB of Boot Flash

is incorporated for easy customer inclusion of field-programmable software routines that can be used to

program the main Program and Data Flash memory areas. Both Program and Data Flash memories can be

independently bulk erased or erased in pages. Program Flash page erase size is 1KB. Boot and Data Flash

page erase size is 512 bytes. The Boot Flash memory can also be either bulk or page erased.

A key application-specific feature of the 56F8322 is the inclusion of one Pulse Width Modulator (PWM)

module. This module incorporates three complementary, individually programmable PWM signal output

pairs and is also capable of supporting six independent PWM functions to enhance motor control

functionality. Complementary operation permits programmable dead time insertion, distortion correction

via current sensing by software, and separate top and bottom output polarity control. The up-counter value

is programmable to support a continuously variable PWM frequency. Edge-aligned and center-aligned

synchronous pulse width control (0% to 100% modulation) is supported. The device is capable of

controlling most motor types: ACIM (AC Induction Motors); both BDC and BLDC (Brush and Brushless

DC motors); SRM and VRM (Switched and Variable Reluctance Motors); and stepper motors. The PWM

incorporates fault protection and cycle-by-cycle current limiting with sufficient output drive capability to

directly drive standard optoisolators. A “smoke-inhibit”, write-once protection feature for key parameters

is also included. A patented PWM waveform distortion correction circuit is also provided. Each PWM is

double-buffered and includes interrupt controls to permit integral reload rates to be programmable from

1/2 (center-aligned mode only) to 16. The PWM module provides reference outputs to synchronize the

Analog-to-Digital Converters (ADCs) through Quad Timer C, channel 2.

The 56F8322 incorporates one Quadrature Decoder capable of capturing all four transitions on the

two-phase inputs, permitting generation of a number proportional to actual position. Speed computation

capabilities accommodate both fast- and slow-moving shafts. An integrated watchdog timer in the

Quadrature Decoder can be programmed with a time-out value to alarm when no shaft motion is detected.

Each input is filtered to ensure only true transitions are recorded.

This controller also provides a full set of standard programmable peripherals that include two Serial

Communications Interfaces (SCIs), two Serial Peripheral Interfaces (SPIs), two Quad Timers and

FlexCAN. Any of these interfaces can be used as General Purpose Input/Outputs (GPIOs) if that function

is not required. A Flex Controller Area Network interface (CAN Version 2.0 B-compliant) and an internal

interrupt controller are also a part of the 56F8322.

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12V1 HCS12 Microcontroller IC 16-Bit 25MHz 64KB (64K x 8) FLASH 32-LQFP (7x7)

Introduction

The MC9S12G-Family is an optimized, automotive, 16-bit microcontroller product line focused on

low-cost, high-performance, and low pin-count. This family is intended to bridge between high-end 8-bit

microcontrollers and high-performance 16-bit microcontrollers, such as the MC9S12XS-Family. The

MC9S12G-Family is targeted at generic automotive applications requiring CAN or LIN/J2602

communication. Typical examples of these applications include body controllers, occupant detection, door

modules, seat controllers, RKE receivers, smart actuators, lighting modules, and smart junction boxes.

The MC9S12G-Family uses many of the same features found on the MC9S12XS- and MC9S12P-Family,

including error correction code (ECC) on flash memory, a fast analog-to-digital converter (ADC) and a

frequency modulated phase locked loop (IPLL) that improves the EMC performance. 

The MC9S12G-Family is optimized for lower program memory sizes down to 16k. In order to simplify

customer use it features an EEPROM with a small 4 bytes erase sector size.

The MC9S12G-Family deliver all the advantages and efficiencies of a 16-bit MCU while retaining the low

cost, power consumption, EMC, and code-size efficiency advantages currently enjoyed by users of NXP’s

existing 8-bit and 16-bit MCU families. Like the MC9S12XS-Family, the MC9S12G-Family run 16-bit

wide accesses without wait states for all peripherals and memories. The MC9S12G-Family is available in

100-pin LQFP, 64-pin LQFP, 48-pin LQFP/QFN, 32-pin LQFP and 20-pin TSSOP package options and

aims to maximize the amount of functionality especially for the lower pin count packages. In addition to

the I/O ports available in each module, further I/O ports are available with interrupt capability allowing

wake-up from stop or wait modes.

Chip-Level Features

On-chip modules available within the family include the following features:

• S12 CPU core

• Up to 240 Kbyte on-chip flash with ECC

• Up to 4 Kbyte EEPROM with ECC

• Up to 11 Kbyte on-chip SRAM

• Phase locked loop (IPLL) frequency multiplier with internal filter

• 4–16 MHz amplitude controlled Pierce oscillator

• 1 MHz internal RC oscillator

• Timer module (TIM) supporting up to eight channels that provide a range of 16-bit input capture,

output compare, counter, and pulse accumulator functions

• Pulse width modulation (PWM) module with up to eight x 8-bit channels

• Up to 16-channel, 10 or 12-bit resolution successive approximation analog-to-digital converter

(ADC)

• Up to two 8-bit digital-to-analog converters (DAC)

• Up to one 5V analog comparator (ACMP)

• Up to three serial peripheral interface (SPI) modules

• Up to three serial communication interface (SCI) modules supporting LIN communications

• Up to one multi-scalable controller area network (MSCAN) module (supporting CAN protocol

2.0A/B)

• On-chip voltage regulator (VREG) for regulation of input supply and all internal voltages

• Autonomous periodic interrupt (API)

• Precision fixed voltage reference for ADC conversions

• Optional reference voltage attenuator module to increase ADC accuracy

How do you identify which pin is pin 1 of an IC integrated circuit chip? |ICONECHIP

For more product unboxing videos, please click on the link

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56800E 56F8xxx Microcontroller IC 16-Bit 32MHz 32KB (16K x 16) FLASH 32-LQFP (7x7)

56F8033/56F8023 Description

The 56F8033/56F8023 is a member of the 56800E core-based family of Digital Signal Controllers

(DSCs). It combines, on a single chip, the processing power of a DSP and the functionality of a

microcontroller with a flexible set of peripherals to create an extremely cost-effective solution. Because

of its low cost, configuration flexibility, and compact program code, the 56F8033/56F8023 is well-suited

for many applications. The 56F8033/56F8023 includes many peripherals that are especially useful for

industrial control, motion control, home appliances, general-purpose inverters, smart sensors, fire and

security systems, switched-mode power supply, power management, and medical monitoring

applications.

The 56800E core is based on a dual Harvard-style architecture consisting of three execution units

operating in parallel, allowing as many as six operations per instruction cycle. The MCU-style

programming model and optimized instruction set allow straightforward generation of efficient, compact

DSP and control code. The instruction set is also highly efficient for C compilers to enable rapid

development of optimized control applications.

The 56F8033/56F8023 supports program execution from internal memories. Two data operands can be

accessed from the on-chip data RAM per instruction cycle. The 56F8033/56F8023 also offers up to 26

General-Purpose Input/Output (GPIO) lines, depending on peripheral configuration.

The 56F8033 Digital Signal Controller includes 64KB of Program Flash and 8KB of Unified

Data/Program RAM. The 56F8023 Digital Signal Controller includes 32KB of Program Flash and 4KB of

Unified Data/Program RAM. Program Flash memory can be independently bulk erased or erased in pages.

Program Flash page erase size is 512 Bytes (256 Words). 

56F8033/56F8023 Features

Digital Signal Controller Core

• Efficient 16-bit 56800E family Digital Signal Controller (DSC) engine with dual Harvard architecture

• As many as 32 Million Instructions Per Second (MIPS) at 32MHz core frequency

• Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC)

• Four 36-bit accumulators, including extension bits

• 32-bit arithmetic and logic multi-bit shifter

• Parallel instruction set with unique DSP addressing modes

• Hardware DO and REP loops

• Three internal address buses

• Four internal data buses

• Instruction set supports both DSP and controller functions

• Controller-style addressing modes and instructions for compact code

• Efficient C compiler and local variable support

• Software subroutine and interrupt stack with depth limited only by memory

• JTAG/Enhanced On-Chip Emulation (OnCE) for unobtrusive, processor speed-independent, real-time

debugging

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