NXP USA Inc.

56800E 56F8xxx Microcontroller IC 16-Bit 32MHz 32KB (16K x 16) FLASH 64-LQFP (10x10)

56F8037/56F8027 Description

The 56F8037/56F8027 is a member of the 56800E core-based family of Digital Signal Controllers (DSCs).

It combines, on a single chip, the processing power of a DSP and the functionality of a microcontroller

with a flexible set of peripherals to create an extremely cost-effective solution. Because of its low cost,

configuration flexibility, and compact program code, the 56F8037/56F8027 is well-suited for many

applications. The 56F8037/56F8027 includes many peripherals that are especially useful for industrial

control, motion control, home appliances, general purpose inverters, smart sensors, fire and security

systems, switched-mode power supply, power management, and medical monitoring applications.

The 56800E core is based on a dual Harvard-style architecture consisting of three execution units

operating in parallel, allowing as many as six operations per instruction cycle. The MCU-style

programming model and optimized instruction set allow straightforward generation of efficient, compact

DSP and control code. The instruction set is also highly efficient for C compilers to enable rapid

development of optimized control applications.

The 56F8037/56F8027 supports program execution from internal memories. Two data operands can be

accessed from the on-chip data RAM per instruction cycle. The 56F8037/56F8027 also offers up to 53

General Purpose Input/Output (GPIO) lines, depending on peripheral configuration.

The 56F8037 Digital Signal Controller includes 64KB of Program Flash and 8KB of Unified

Data/Program RAM. The 56F8027 Digital Signal Controller includes 32KB of Program Flash and 4KB of

Unified Data/Program RAM. Program Flash memory can be independently bulk erased or erased in pages.

Program Flash page erase size is 512 Bytes (256 Words).

A full set of programmable peripherals—PWM, ADCs, QSCIs, QSPIs, I2C, PITs, Quad Timers, DACs

and analog comparators—supports various applications. Each peripheral can be independently shut down

to save power. Any pin in these peripherals can also be used as General Purpose Input/Outputs (GPIOs).

56F8037/56F8027 Features

Digital Signal Controller Core

• Efficient 16-bit 56800E family Digital Signal Controller (DSC) engine with dual Harvard architecture

• As many as 32 Million Instructions Per Second (MIPS) at 32MHz core frequency

• Single-cycle 16  16-bit parallel Multiplier-Accumulator (MAC)

• Four 36-bit accumulators, including extension bits

• 32-bit arithmetic and logic multi-bit shifter

• Parallel instruction set with unique DSP addressing modes

• Hardware DO and REP loops

• Three internal address buses

• Four internal data buses

• Instruction set supports both DSP and controller functions

• Controller-style addressing modes and instructions for compact code

• Efficient C compiler and local variable support

• Software subroutine and interrupt stack with depth limited only by memory

• JTAG/Enhanced On-Chip Emulation (OnCE) for unobtrusive, processor speed-independent, real-time 

12V1 HCS12 Microcontroller IC 16-Bit 25MHz 16KB (16K x 8) FLASH 32-LQFP (7x7)

Introduction

The MC9S12G-Family is an optimized, automotive, 16-bit microcontroller product line focused on

low-cost, high-performance, and low pin-count. This family is intended to bridge between high-end 8-bit

microcontrollers and high-performance 16-bit microcontrollers, such as the MC9S12XS-Family. The

MC9S12G-Family is targeted at generic automotive applications requiring CAN or LIN/J2602

communication. Typical examples of these applications include body controllers, occupant detection, door

modules, seat controllers, RKE receivers, smart actuators, lighting modules, and smart junction boxes.

The MC9S12G-Family uses many of the same features found on the MC9S12XS- and MC9S12P-Family,

including error correction code (ECC) on flash memory, a fast analog-to-digital converter (ADC) and a

frequency modulated phase locked loop (IPLL) that improves the EMC performance.

The MC9S12G-Family is optimized for lower program memory sizes down to 16k. In order to simplify

customer use it features an EEPROM with a small 4 bytes erase sector size.

The MC9S12G-Family deliver all the advantages and efficiencies of a 16-bit MCU while retaining the low

cost, power consumption, EMC, and code-size efficiency advantages currently enjoyed by users of NXP’s

existing 8-bit and 16-bit MCU families. Like the MC9S12XS-Family, the MC9S12G-Family run 16-bit

wide accesses without wait states for all peripherals and memories. The MC9S12G-Family is available in

100-pin LQFP, 64-pin LQFP, 48-pin LQFP/QFN, 32-pin LQFP and 20-pin TSSOP package options and

aims to maximize the amount of functionality especially for the lower pin count packages. In addition to

the I/O ports available in each module, further I/O ports are available with interrupt capability allowing

wake-up from stop or wait modes.

Chip-Level Features

On-chip modules available within the family include the following features:

• S12 CPU core

• Up to 240 Kbyte on-chip flash with ECC

• Up to 4 Kbyte EEPROM with ECC

• Up to 11 Kbyte on-chip SRAM

• Phase locked loop (IPLL) frequency multiplier with internal filter

• 4–16 MHz amplitude controlled Pierce oscillator

• 1 MHz internal RC oscillator

• Timer module (TIM) supporting up to eight channels that provide a range of 16-bit input capture,

output compare, counter, and pulse accumulator functions

• Pulse width modulation (PWM) module with up to eight x 8-bit channels

• Up to 16-channel, 10 or 12-bit resolution successive approximation analog-to-digital converter

(ADC)

• Up to two 8-bit digital-to-analog converters (DAC)

• Up to one 5V analog comparator (ACMP)

• Up to three serial peripheral interface (SPI) modules

• Up to three serial communication interface (SCI) modules supporting LIN communications

• Up to one multi-scalable controller area network (MSCAN) module (supporting CAN protocol

2.0A/B)

• On-chip voltage regulator (VREG) for regulation of input supply and all internal voltages

• Autonomous periodic interrupt (API)

• Precision fixed voltage reference for ADC conversions

• Optional reference voltage attenuator module to increase ADC accuracy

S12Z S12 MagniV Microcontroller IC 16-Bit 32MHz 128KB (128K x 8) FLASH 48-LQFP (7x7)

Introduction

The MC9S12ZVC-Family is a new member of the S12 MagniV product line integrating a battery level

(12V) voltage regulator, supply voltage monitoring, high voltage inputs and a CAN physical interface. It's

primarily targeting at CAN nodes like sensors, switch panels or small actuators. It offers various

low-power modes and wakeup management to address state of the art power consumption requirements.

Some members of the MC9S12ZVC-Family are also offered for high temperature applications requiring

AEC-Q100 Grade 0 (-40℃ to +150C ambient operating temperature range).

The MC9S12ZVC-Family is based on the enhanced performance, linear address space S12Z core and

delivers an optimized solution with the integration of severalkey system components into a single device,

optimizing system architecture and achieving significant space savings.

Chip-Level Features

On-chip modules available within the family include the following features:

·S12Z CPU core

·Up to 192 Kbyte on-chip flash with ECC

·Up to 2 Kbyte EEPROM with ECC

·Up to 12Kbyte on-chip SRAM with ECC

·Phase locked loop (IPLL) frequency multiplier with internal filter

·1 MHz internalRC oscillator with +/-1.3% accuracy over rated temperature range

·4-20MHz amplitude controlled pierce oscillator

·Internal COP (watchdog) module

·Analog-to-digital converter (ADC) with 12-bit resolution and up to 16 channels available on

external pins

·Two analog comparators (ACMP) with rail-to-rail inputs

·One 8-bit 5V digita1-to-analog converter(DAC)

·Up to two serial peripheral interface (SPI) modules

·Up to two serial communication interface(SCI) modules

·SENT Transmitter Interface

·MSCAN(1Mbit/s,CAN 2.0 A, B software compatible) module

·One on-chip CAN physical layer module

·8-channel timer module (TIM0) with input capture/output compare

·4-channel timer module (TIM1) with input capture/output compare (fast max 64MHz)

·Inter-IC (IIC) module

·4-channe1 16-bit Pulse Width Modulation module (PWM0)

·4-channe1 16-bit Pulse Width Modulation module (PWM1) (fast max 64MHz)

·On-chip voltage regulator (VREG) for regulation of input supply and all internal voltages

·Autonomous periodic interrupt (API), supports cyclic wakeup from Stop mode

·Four pins to support 25 mA drive strength to VSsx

·One pin to support 20 mA drive strength from VDDX (EVDD)

·Two High Voltage Input (HVI) pins

·Supply Vsup monitoring with warning

·On-chip temperature sensor, temperature value can be measured with ADC or can generate a high

temperature interrupt

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