NXP USA Inc.

12V1 HCS12 Microcontroller IC 16-Bit 25MHz 32KB (32K x 8) FLASH 48-LQFP (7x7)

Introduction

The MC9S12G-Family is an optimized, automotive, 16-bit microcontroller product line focused on

low-cost, high-performance, and low pin-count. This family is intended to bridge between high-end 8-bit

microcontrollers and high-performance 16-bit microcontrollers, such as the MC9S12XS-Family. The

MC9S12G-Family is targeted at generic automotive applications requiring CAN or LIN/J2602

communication. Typical examples of these applications include body controllers, occupant detection, door

modules, seat controllers, RKE receivers, smart actuators, lighting modules, and smart junction boxes.

The MC9S12G-Family uses many of the same features found on the MC9S12XS- and MC9S12P-Family,

including error correction code (ECC) on flash memory, a fast analog-to-digital converter (ADC) and a

frequency modulated phase locked loop (IPLL) that improves the EMC performance. 

The MC9S12G-Family is optimized for lower program memory sizes down to 16k. In order to simplify

customer use it features an EEPROM with a small 4 bytes erase sector size.

The MC9S12G-Family deliver all the advantages and efficiencies of a 16-bit MCU while retaining the low

cost, power consumption, EMC, and code-size efficiency advantages currently enjoyed by users of NXP’s

existing 8-bit and 16-bit MCU families. Like the MC9S12XS-Family, the MC9S12G-Family run 16-bit

wide accesses without wait states for all peripherals and memories. The MC9S12G-Family is available in

100-pin LQFP, 64-pin LQFP, 48-pin LQFP/QFN, 32-pin LQFP and 20-pin TSSOP package options and

aims to maximize the amount of functionality especially for the lower pin count packages. In addition to

the I/O ports available in each module, further I/O ports are available with interrupt capability allowing

wake-up from stop or wait modes.

Chip-Level Features

On-chip modules available within the family include the following features:

• S12 CPU core

• Up to 240 Kbyte on-chip flash with ECC

• Up to 4 Kbyte EEPROM with ECC

• Up to 11 Kbyte on-chip SRAM

• Phase locked loop (IPLL) frequency multiplier with internal filter

• 4–16 MHz amplitude controlled Pierce oscillator

• 1 MHz internal RC oscillator

• Timer module (TIM) supporting up to eight channels that provide a range of 16-bit input capture,

output compare, counter, and pulse accumulator functions

• Pulse width modulation (PWM) module with up to eight x 8-bit channels

• Up to 16-channel, 10 or 12-bit resolution successive approximation analog-to-digital converter

(ADC)

• Up to two 8-bit digital-to-analog converters (DAC)

• Up to one 5V analog comparator (ACMP)

• Up to three serial peripheral interface (SPI) modules

• Up to three serial communication interface (SCI) modules supporting LIN communications

• Up to one multi-scalable controller area network (MSCAN) module (supporting CAN protocol

2.0A/B)

• On-chip voltage regulator (VREG) for regulation of input supply and all internal voltages

• Autonomous periodic interrupt (API)

• Precision fixed voltage reference for ADC conversions

• Optional reference voltage attenuator module to increase ADC accuracy

HCS12X HCS12X Microcontroller IC 16-Bit 80MHz 256KB (256K x 8) FLASH 80-QFP (14x14)

Introduction

The MC9S12XD family will retain the low cost, power consumption, EMC and code-size efficiency

advantages currently enjoyed by users of Freescale's existing 16-Bit MC9S12 MCU Family.

Based around an enhanced S12 core, the MC9S12XD family will deliver 2 to 5 times the performance of

a 25-MHz S12 whilst retaining a high degree of pin and code compatibility with the S12.

The MC9S12XD family introduces the performance boosting XGATE module. Using enhanced DMA

functionality, this parallel processing module offloads the CPU by providing high-speed data processing

and transfer between peripheral modules, RAM, Flash EEPROM and I/O ports. Providing up to 80 MIPS

of performance additional to the CPU, the XGATE can access all peripherals, Flash EEPROM and the

RAM block.

The MC9S12XD family is composed of standard on-chip peripherals including up to 512 Kbytes of Flash

EEPROM, 32 Kbytes of RAM, 4 Kbytes of EEPROM, six asynchronous serial communications interfaces

(SCI), three serial peripheral interfaces (SPI), an 8-channel IC/OC enhanced capture timer, an 8-channel,

10-bit analog-to-digital converter, a 16-channel, 10-bit analog-to-digital converter, an 8-channel

pulse-width modulator (PWM), five CAN 2.0 A, B software compatible modules (MSCAN12), two

inter-IC bus blocks, and a periodic interrupt timer. The MC9S12XD family has full 16-bit data paths

throughout.

The non-multiplexed expanded bus interface available on the 144-pin versions allows an easy interface to

external memories

The inclusion of a PLL circuit allows power consumption and performance to be adjusted to suit

operational requirements. System power consumption can be further improved with the new “fast exit from

stop mode” feature.

In addition to the I/O ports available in each module, up to 25 further I/O ports are available with interrupt

capability allowing wake-up from stop or wait mode.

Family members in 144-pin LQFP will be available with external bus interface and parts in 112-pin LQFP

or 80-pin QFP package without external bus interface. See Appendix E Derivative Differencesfor package

options.

MC9S12XD/B/A Family Features

• HCS12X Core

— 16-bit HCS12X CPU

– Upward compatible with MC9S12 instruction set

– Interrupt stacking and programmer’s model identical to MC9S12

– Instruction queue

– Enhanced indexed addressing

– Enhanced instruction set

— EBI (external bus interface)

— MMC (module mapping control)

— INT (interrupt controller)

— DBG (debug module to monitor HCS12X CPU and XGATE bus activity)

— BDM (background debug mode)

• XGATE (peripheral coprocessor)

— Parallel processing module off loads the CPU by providing high-speed data processing and

transfer

— Data transfer between Flash EEPROM, RAM, peripheral modules, and I/O ports

• PIT (periodic interrupt timer)

— Four timers with independent time-out periods

— Time-out periods selectable between 1 and 224 bus clock cycles

• CRG (clock and reset generator)

— Low noise/low power Pierce oscillator

— PLL

— COP watchdog

— Real time interrupt

— Clock monitor

— Fast wake-up from stop mode

• Port H & Port J with interrupt functionality

— Digital filtering

— Programmable rising or falling edge trigger

• Memory

— 512, 256 and 128-Kbyte Flash EEPROM

— 4 and 2-Kbyte EEPROM

— 32, 16 and 12-Kbyte RAM

• One 16-channel and one 8-channel ADC (analog-to-digital converter)

— 10-bit resolution

— External and internal conversion trigger capabilityFiveFourTwo 1M bit per second,

CAN 2.0 A, B software compatible modules

— Five receive and three transmit buffers

— Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit, or 8 x 8 bit

— Four separate interrupt channels for Rx, Tx, error, and wake-up

— Low-pass filter wake-up function

— Loop-back for self-test operation

• ECT (enhanced capture timer)

— 16-bit main counter with 7-bit prescaler

— 8 programmable input capture or output compare channels

— Four 8-bit or two 16-bit pulse accumulators

• 8 PWM (pulse-width modulator) channels

— Programmable period and duty cycle

— 8-bit 8-channel or 16-bit 4-channel

— Separate control for each pulse width and duty cycle

— Center-aligned or left-aligned outputs

— Programmable clock select logic with a wide range of frequencies

— Fast emergency shutdown input

• Serial interfaces

— SixFourTwo asynchronous serial communication interfaces (SCI) with additional LIN support

and selectable IrDA 1.4 return-to-zero-inverted (RZI) format with programmable pulse width

— ThreeTwo Synchronous Serial Peripheral Interfaces (SPI)

• TwoOne IIC (Inter-IC bus) Modules

— Compatible with IIC bus standard

— Multi-master operation

— Software programmable for one of 256 different serial clock frequencies

• On-Chip Voltage Regulator

— Two parallel, linear voltage regulators with bandgap reference

— Low-voltage detect (LVD) with low-voltage interrupt (LVI)

— Power-on reset (POR) circuit

— 3.3-V–5.5-V operation

— Low-voltage reset (LVR)

— Ultra low-power wake-up timer

• 144-pin LQFP, 112-pin LQFP, and 80-pin QFP packages

— I/O lines with 5-V input and drive capability

— Input threshold on external bus interface inputs switchable for 3.3-V or 5-V operation

— 5-V A/D converter inputs

— Operation at 80 MHz equivalent to 40-MHz bus speed

• Development support

— Single-wire background debug™ mode (BDM)

— Four on-chip hardware breakpoints

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56800E 56F8xxx Microcontroller IC 16-Bit 60MHz 64KB (32K x 16) FLASH 48-LQFP (7x7)

Introduction

The MC56F825x/MC56F824x is a member of Freescale’s family of digital signal controllers (DSCs)

based on the 56800E core. It combines, on a single chip, DSP processing power and microcontroller

functionality with a flexible set of peripherals, creating a cost-effective solution. Because of its low cost, 

configuration flexibility, and compact program code, it is well-suited for many consumer and industrial 

applications, including:

• Industrial control

• Home appliances

• Smart sensors

• Fire and security systems

• Solar inverters

• Battery chargers and management

• Switched-mode power supplies and management

• Power metering

• Motor control (ACIM, BLDC, PMSM, SR, and stepper)

• Handheld power tools

• Arc detection

• Medical devices/equipment

• Instrumentation

• Lighting ballast

The 56800E core is based on a dual Harvard-style architecture consisting of three execution units

operating in parallel, allowing as many as six operations per instruction cycle. The MCU-style

programming model and optimized instruction set allow straightforward generation of efficient, compact

DSP and control code. The instruction set is also highly efficient for C compilers to enable rapid

development of optimized control applications.

The MC56F825x/MC56F824x supports program execution from internal memories. Two data operands

per instruction cycle can be accessed from the on-chip data RAM. A full set of programmable peripherals

supports various applications. Each peripheral can be independently shut down to save power. Any pin

except power pins can also be configured as General Purpose Input/Output (GPIO).

Chip-level features

On-chip features include:

• 60 MHz operation frequency

• DSP and MCU functionality in a unified, C-efficient architecture

• On-chip memory

— 56F8245/46: 48 KB (24K  16) flash memory; 6 KB (3K  16) unified data/program RAM

— 56F8247: 48 KB (24K  16) flash memory; 8 KB (4K  16) unified data/program RAM

— 56F8255/56/57: 64 KB (32K  16) flash memory; 8 KB (4K  16) unified data/program RAM

• eFlexPWM with up to 9 channels, including 6 channels with high (520 ps) resolution NanoEdge

placement

• Two 8-channel, 12-bit analog-to-digital converters (ADCs)

— Dynamic 2 and 4 programmable amplifier

— Conversion time as short as 600 ns

— Input current-injection protection

• Three analog comparators with integrated 5-bit DAC references

• Cyclic redundancy check (CRC) generator

• Two high-speed queued serial communication interface (QSCI) modules with LIN slave

functionality

• Queued serial peripheral interface (QSPI) module

• Two SMBus-compatible inter-integrated circuit (I2C) ports

• Freescale’s scalable controller area network (MSCAN) 2.0 A/B module

• Two 16-bit quad timers (2  4 16-bit timers)

• Computer operating properly (COP) watchdog module

• On-chip relaxation oscillator: 8 MHz (400 kHz at standby mode)

• Crystal/resonator oscillator

• Integrated power-on reset (POR) and low-voltage interrupt (LVI) and brown-out reset module

• Inter-module crossbar connection

• Up to 54 GPIOs

• 44-pin LQFP, 48-pin LQFP, and 64-pin LQFP packages

• Single supply: 3.0 V to 3.6 V

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